- Aug 01, 2023
-
-
Dmitry Baryshkov authored
The global clock controller on MDM9615 uses external CXO and PLL7 clocks. Split the qcom,gcc-mdm9615 to the separate schema file. Reviewed-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by:
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20230512211727.3445575-4-dmitry.baryshkov@linaro.org Signed-off-by:
Bjorn Andersson <andersson@kernel.org>
-
Dmitry Baryshkov authored
The header file for qcom,lcc-mdm9615 and qcom,lcc-msm8960 is the same (as well as the drivers). Drop the qcom,lcc-mdm9615.h in favour of qcom,lcc-msm8960.h Reviewed-by:
-
Dmitry Baryshkov authored
Describe parent clocks used by the LCC on the MDM9615 platform. It is the list as the one for msm8960/apq8064, with only difference being pxo/cxo replacement. Acked-by:
-
Konrad Dybcio authored
SC8280XP, being a partial derivative of SM8350, shares almost the exact same videocc block. Extend the 8350 driver to support the bigger brother. The only notable changes are higher possible frequencies on some clocks and some switcheroo within the XO/sleep registers (probably due to some different board crystal configuration). Reviewed-by:
Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20230703-topic-8280_videocc-v2-2-c88269806269@linaro.org Signed-off-by:
-
Konrad Dybcio authored
SC8280XP reuses the SM8350 video clock controller block, changing just a couple tunables. Docuemnt it. Acked-by:
-
- Jul 28, 2023
-
-
Konrad Dybcio authored
The DISP_CC GDSCs have not been instructed to use the ret registers. Fix that. Fixes: 4a66e76f ("clk: qcom: Add SC8280XP display clock controller") Signed-off-by:
-
- Jul 18, 2023
-
-
Johan Hovold authored
Drivers that enable runtime PM must make sure that the controller is runtime resumed before accessing its registers to prevent the power domain from being disabled. Fixes: 892df019 ("clk: qcom: Add QCS404 TuringCC") Cc: stable@vger.kernel.org # 5.2 Cc: Bjorn Andersson <andersson@kernel.org> Signed-off-by:
Johan Hovold <johan+linaro@kernel.org> Link: https://lore.kernel.org/r/20230718132902.21430-9-johan+linaro@kernel.org Signed-off-by:
-
Johan Hovold authored
Drivers that enable runtime PM must make sure that the controller is runtime resumed before accessing its registers to prevent the power domain from being disabled. Fixes: 8def929c ("clk: qcom: Add modem clock controller driver for SC7180") Cc: stable@vger.kernel.org # 5.7 Cc: Taniya Das <quic_tdas@quicinc.com> Signed-off-by:
-
Johan Hovold authored
Drivers that enable runtime PM must make sure that the controller is runtime resumed before accessing its registers to prevent the power domain from being disabled. Fixes: 6cdef273 ("clk: qcom: Add Q6SSTOP clock controller for QCS404") Cc: stable@vger.kernel.org # 5.5 Signed-off-by:
-
Johan Hovold authored
Drivers that enable runtime PM must make sure that the controller is runtime resumed before accessing its registers to prevent the power domain from being disabled. Fixes: 4ab43d17 ("clk: qcom: Add lpass clock controller driver for SC7280") Cc: stable@vger.kernel.org # 5.16 Cc: Taniya Das <quic_tdas@quicinc.com> Signed-off-by:
-
Johan Hovold authored
Make sure to decrement the runtime PM usage count before returning in case RCG dynamic frequency switch initialisation fails. Fixes: 2a541abd ("clk: qcom: gcc-sc8280xp: Add runtime PM") Cc: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by:
-
Johan Hovold authored
Make sure to decrement the runtime PM usage count before returning in case regmap initialisation fails. Fixes: 90114ca1 ("clk: qcom: add SM8550 DISPCC driver") Cc: stable@vger.kernel.org # 6.3 Cc: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by:
-
Johan Hovold authored
Make sure to decrement the runtime PM usage count before returning in case regmap initialisation fails. Fixes: 16fb89f9 ("clk: qcom: Add support for Display Clock Controller on SM8450") Cc: stable@vger.kernel.org # 6.1 Cc: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by:
-
Johan Hovold authored
To make sure that the controller is runtime resumed and its power domain is enabled before accessing its registers during probe, the synchronous runtime PM interface must be used. Fixes: 8d402594 ("clk: qcom: camcc-sc7180: Use runtime PM ops instead of clk ones") Cc: stable@vger.kernel.org # 5.11 Cc: Stephen Boyd <sboyd@kernel.org> Signed-off-by:
-
- Jul 16, 2023
-
-
Bjorn Andersson authored
This series reshuffles things around, moving the management of SMD RPM bus clocks to the interconnect framework where they belong. This helps us solve a couple of issues: 1. We can work towards unused clk cleanup of RPMCC without worrying about it killing some NoC bus, resulting in the SoC dying. Deasserting actually unused RPM clocks (among other things) will let us achieve "true SoC-wide power collapse states", also known as VDD_LOW and VDD_MIN. 2. We no longer have to keep tons of quirky bus clock ifs in the icc driver. You either have a RPM clock and call "rpm set rate" or you have a single non-RPM clock (like AHB_CLK_SRC) or you don't have any. 3. There's less overhead - instead of going through layers and layers of the CCF, ratesetting comes down to calling max() and sending a single RPM message. ICC is very very dynamic so that's a big plus. The clocks still need to be vaguely described in the clk-smd-rpm driver, as it gives them an initial kickoff, before actually telling RPM to enable DVFS scaling. After RPM receives that command, all clocks that have not been assigned a rate are considered unused and are shut down in hardware, leading to the same issue as described in point 1. We can consider marking them __initconst in the future, but this series is very fat even without that.. Apart from that, it squashes a couple of bugs that really need fixing.. The series is merged through a topic branch to manage the dependencies between interconnect, Qualcomm clocks and Qualcomm SoC.
-
Konrad Dybcio authored
Up until now, we've been aggregating the bandwidth values and only dividing them by the bus width of the source node. This was completely wrong, as different nodes on a given path may (and usually do) have varying bus widths. That in turn, resulted in the calculated clock rates being completely bogus - usually they ended up being much higher, as NoC_A<->NoC_B links are very wide. Since we're not using the aggregate bandwidth value for anything other than clock rate calculations, remodel qcom_icc_bus_aggregate() to calculate the per-context clock rate for a given provider, taking into account the bus width of every individual node. Fixes: 30c8fa3e ("interconnect: qcom: Add MSM8916 interconnect provider driver") Reported-by:
Stephan Gerhold <stephan@gerhold.net> Reviewed-by:
Georgi Djakov <djakov@kernel.org> Link: https://lore.kernel.org/r/20230526-topic-smd_icc-v7-22-09c78c175546@linaro.org Signed-off-by:
-
Konrad Dybcio authored
Currently, we're setting the aggregated-on-provider bandwidth on each node, individually. That is of course incorrect and results in far too high votes. Use the correct values to ensure we're not wasting power. Fixes: 30c8fa3e ("interconnect: qcom: Add MSM8916 interconnect provider driver") Reported-by:
-
Konrad Dybcio authored
Up until now, for some reason we've only been setting bandwidth values on the active-only context. That pretty much meant that RPM could lift all votes when entering sleep mode. Or never sleep at all. That in turn could potentially break things like USB wakeup, as the connection between APSS and SNoC/PNoC would simply be dead. Set the values appropriately. Fixes: 30c8fa3e ("interconnect: qcom: Add MSM8916 interconnect provider driver") Reviewed-by:
-
Konrad Dybcio authored
SMD RPM only provides two buckets, one each for the active-only and active-sleep RPM contexts. Use the correct constant to allocate and operate on them. This will make the qcom,icc.h header no longer work with this driver, mostly because.. it was never meant to! The commit that introduced bucket support to SMD RPM was trying to shove a square into a round hole and it did not work out very well. That said, there are no active users of SMD RPM ICC + qcom,icc.h, so that doesn't hurt. Fixes: dcbce7b0 ("interconnect: qcom: icc-rpm: Support multiple buckets") Reviewed-by:
-
Konrad Dybcio authored
The interconnect bus clocks are now handled within the ICC framework. They still however need to get a kickstart *before* we call clk_smd_rpm_enable_scaling(), or RPM will assume that they should all be running at 0 kHz and the system will inevitably die. Separate them out to ensure such a kickstart can still take place. As a happy accident, the file got smaller: Total: Before=41951, After=41555, chg -0.94% Signed-off-by:
Stephen Boyd <sboyd@kernel.org> Acked-by:
-
Konrad Dybcio authored
The sole purpose of bus clocks that were previously registered with rpmcc was to convey the aggregated bandwidth to RPM. There's no good reason to keep them outside the interconnect framework, as it only adds to the plentiful complexity. Add the required code to handle these clocks from within SMD RPM ICC. RPM-owned bus clocks are no longer considered a thing, but sadly we have to allow for the existence of HLOS-owned bus clocks, as some (mostly older) SoCs (ab)use these for bus scaling (e.g. MSM8998 and &mmcc AHB_CLK_SRC). This in turn is trivially solved with a single *clk, which is filled and used iff qp.bus_clk_desc is absent and we have a "bus" clock-names entry in the DT node. This change should(tm) be fully compatible with all sorts of old Device Trees as far as the interconnect functionality goes (modulo abusing bus clock handles or wrongly using the qcom,icc.h binding, but that's a mistake in and of itself). Reviewed-by:
-
Konrad Dybcio authored
Assign the necessary definitions to migrate to the new bus clock handling mechanism. Reviewed-by:
-
Konrad Dybcio authored
Assign the necessary definitions to migrate to the new bus clock handling mechanism. Reviewed-by:
-
Konrad Dybcio authored
Assign the necessary definitions to migrate to the new bus clock handling mechanism. Reviewed-by:
-
Konrad Dybcio authored
Assign the necessary definitions to migrate to the new bus clock handling mechanism. Reviewed-by:
-
Konrad Dybcio authored
Assign the necessary definitions to migrate to the new bus clock handling mechanism. Signed-off-by:
-
Konrad Dybcio authored
Assign the necessary definitions to migrate to the new bus clock handling mechanism. Reviewed-by:
-
Konrad Dybcio authored
Add the definitions for RPM bus clocks that will be used by many different platforms. Reviewed-by:
-
Konrad Dybcio authored
Introduce qcom_icc_rpm_set_bus_rate() in preparation for handling RPM clock resources within the interconnect framework. This lets us greatly simplify all of the code handling, as setting the rate comes down to: u32 rate_khz = max(clk.sleep_rate, clk.active_rate, clk_a.active_rate) write_to_rpm(clock.description, rate_khz); Reviewed-by:
-
Konrad Dybcio authored
smd-rpm.h is not very useful as-is and both files are always included anyway.. Combine them. Reviewed-by:
-
Konrad Dybcio authored
Currently the header does not provide all the required dependencies. Fix it. Signed-off-by:
-
Konrad Dybcio authored
The downstream kernel employs the concept of "keeping the bus alive" by voting for the minimum (XO/19.2MHz) rate at all times on certain (well, most) buses. This is a very important thing to have, as if we either have a lackluster/wrong DT that doesn't specify a (high enough) vote on a certain bus, we may lose access to the entire bus altogether. This is very apparent when we only start introducing interconnect support on a given platform and haven't yet introduced voting on all peripherals. The same can happen if we only have a single driver casting a vote on a certain bus and that driver exits/crashes/suspends. The keepalive vote is limited to the ACTIVE bucket, as keeping a permanent vote on the SLEEP one could prevent the platform from properly entering low power mode states. Introduce the very same concept, with a slight twist: the vendor kernel checks whether the rate is zero before setting the minimum vote, but that's rather silly, as in doing so we're at the mercy of CCF. Instead, explicitly clamp the rates to always be >= 19.2 MHz for providers with keep_alive=true. Reviewed-by:
-
Stephan Gerhold authored
icc_smd_rpm will do bus clock votes itself rather than taking the unnecessary detour through the clock subsystem. However, it can only do that after the clocks have been handed off and scaling has been enabled in the RPM in clk-smd-rpm. Move the icc_smd_rpm registration from smd-rpm.c to clk-smd-rpm.c to avoid any possible races. icc_smd_rpm gets the driver data from the smd-rpm device, so still register the platform device on the smd-rpm parent device. Signed-off-by:
-
Konrad Dybcio authored
In preparation for handling the bus clocks in the icc driver, carve out some defines and a struct definition to the common rpm header. Reviewed-by:
-
Konrad Dybcio authored
Use tabs for defines to make things spaced consistently. Signed-off-by:
-
Konrad Dybcio authored
Add a preprocessor define to indicate the number of RPM contexts/states. Signed-off-by:
-
Konrad Dybcio authored
The SMD RPM interconnect driver requires different icc tags to the RPMh driver. Add bindings to reflect that. Acked-by:
-
- Jul 10, 2023
-
-
Manivannan Sadhasivam authored
With the minimal system suspend support in place for the PCIe driver that keeps the interconnect path voted, the ALWAYS_ON flag can now be dropped. Also, the pwrsts PWRSTS_RET_ON flag should be used to allow the GDSCs to enter the retention state when the parent domain get's turned off during system suspend. Signed-off-by:
Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20230707075926.11726-1-manivannan.sadhasivam@linaro.org Signed-off-by:
-
Danila Tikhonov authored
Set .flags = CLK_OPS_PARENT_ENABLE to fix "gcc_sdcc2_apps_clk_src: rcg didn't update its configuration" error. Fixes: a808d58d ("clk: qcom: Add Global Clock Controller (GCC) driver for SM7150") Signed-off-by:
Danila Tikhonov <danila@jiaxyga.com> Reviewed-by:
-
Taniya Das authored
Update my email address from the defunct codeaurora.org domain to the current quicinc.com domain. Signed-off-by:
Taniya Das <quic_tdas@quicinc.com> Acked-by:
Rob Herring <robh@kernel.org> Reviewed-by:
Jeffrey Hugo <quic_jhugo@quicinc.com> Link: https://lore.kernel.org/r/20230627173123.9221-1-quic_tdas@quicinc.com Signed-off-by:
-
