- Jan 30, 2023
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Philippe Schenker authored
Add new carrier board device tree Yavia for the Verdin iMX8M Plus SoM. Yavia is a compact carrier board providing easy access to the most common features of the Verdin family. The intended use of the carrier board is application software development. The board is compatible with all current and future Verdin SoMs. Co-developed-by:
Aishwarya Kothari <aishwarya.kothari@toradex.com> Signed-off-by:
Philippe Schenker <philippe.schenker@toradex.com> Signed-off-by:
Shawn Guo <shawnguo@kernel.org>
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Philippe Schenker authored
Add new carrier board device tree Yavia for the Verdin iMX8M Mini SoM. Yavia is a compact carrier board providing easy access to the most common features of the Verdin family. The intended use of the carrier board is application software development. The board is compatible with all current and future Verdin SoMs. Co-developed-by:
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Krzysztof Kozlowski authored
Use generic "mcu" node name for rave-sp node, as recommended by Devicetree specification. Signed-off-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by:
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- Jan 26, 2023
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Philippe Schenker authored
Follow the change that has been done on imx8mm-verdin-dev.dtsi and remove the include from dahlia to be consistent. Put back all nodes that previously had been included. Signed-off-by:
Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by:
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Philippe Schenker authored
Inheriting the dahlia devicetree leads to inheriting certain settings for the audio-codec that are not correct and hence the dt schema check failing. Remove that include and put all nodes back that had been included. Signed-off-by:
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Marek Vasut authored
The VSELECT pin is configured as MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT and not as a GPIO, drop the bogus sd-vsel-gpios property as the eSDHC block handles the VSELECT pin on its own. Signed-off-by:
Marek Vasut <marex@denx.de> Reviewed-by:
Frieder Schrempf <frieder.schrempf@kontron.de> Signed-off-by:
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Marek Vasut authored
The VSELECT pin is configured as MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT and not as a GPIO, drop the bogus sd-vsel-gpios property as the eSDHC block handles the VSELECT pin on its own. Signed-off-by:
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Marek Vasut authored
The VSELECT pin is configured as MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT and not as a GPIO, drop the bogus sd-vsel-gpios property as the eSDHC block handles the VSELECT pin on its own. Signed-off-by:
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Marek Vasut authored
Use PLL1_80M instead of PLL3 to drive UART2 clock divided down to 80 MHz instead of 64 MHz to obtain suitable block clock for exact 4 Mbdps, which is the maximum supported baud rate by the muRata 2AE BT UART. The difference here is that at 64 MHz UART block clock, the clock with are divided by 16 (due to oversampling) to 4 MHz and the baud rate generator then needs to be set to UBIR+1/UBMR+1 = 1/1 to yield 4 Mbdps . In case of 80 MHz UART block clock divided by 16 to 5 MHz, the baud rate generator needs to be set to UBIR+1/UBMR+1 = 4/5 to yield 4 Mbdps . Both options are valid and yield the same result, except using the PLL1_80M output requires fewer clock tree changes, since the PLL1 already generates the 80 MHz usable for UART, which frees the PLL3 for other uses. Suggested-by:
Christoph Niedermaier <cniedermaier@dh-electronics.com> Signed-off-by:
Fabio Estevam <festevam@denx.de> Signed-off-by:
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Adam Ford authored
Beacon Embedded has an i.MX8M Plus development kit which consists of a SOM + baseboard. The SOM includes Bluetooth, WiFi, QSPI, eMMC, and one Ethernet PHY. The baseboard includes audio, HDMI, USB-C Dual Role port, USB Hub with five ports, a PCIe slot, and a second Ethernet PHY. Signed-off-by:
Adam Ford <aford173@gmail.com> Signed-off-by:
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Marco Felsch authored
Commit c8713352 ("arm64: dts: imx8mm-evk: Enable pca6416 on i2c3 bus") says that the assembled expander is a PCA6416 and not a TCA6416. No functional change since the driver handles both expanders the same way. Signed-off-by:
Marco Felsch <m.felsch@pengutronix.de> Signed-off-by:
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Haibo Chen authored
Add ADC support for imx93-11x11-evk board. Signed-off-by:
Haibo Chen <haibo.chen@nxp.com> Signed-off-by:
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Marek Vasut authored
Reorder the PCIe clock in DT to match YAML DT schema. No functional change. Signed-off-by:
Richard Zhu <hongxing.zhu@nxp.com> Signed-off-by:
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Marek Vasut authored
Move the PCIe clock-names property from various DTs into SoC dtsi to reduce duplication. In case of a couple of boards, reorder the clock so they match the order in yaml DT bindings. Reviewed-by: Alexander Stein <alexander.stein@ew.tq-group.com> # imx8mq.dtsi, imx8mq-tqma8mq-mba8mx.dts Signed-off-by:
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Marek Vasut authored
Move the PCIe clock-names property from various DTs into SoC dtsi to reduce duplication. In case of a couple of boards, reorder the clock so they match the order in yaml DT bindings. Reviewed-by: Alexander Stein <alexander.stein@ew.tq-group.com> # imx8mm.dtsi, imx8mm-tqma8mqml-mba8mx.dts Signed-off-by:
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Marcel Ziswiler authored
Any other of our modules calls it key-wakeup rather than button-wakeup so let us stick to that. Signed-off-by:
Marcel Ziswiler <marcel.ziswiler@toradex.com> Signed-off-by:
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Michael Walle authored
Now that it is finally possible to get the MAC addresses from the OTP memory, use it to set the addresses of the network devices. There are 8 reserved MAC addresses in total per board. Distribute them as follows: +----------+------+------+------+------+------+ | | var1 | var2 | var3 | var4 | kbox | +----------+------+------+------+------+------+ | enetc #0 | +0 | | | +0 | +0 | | enetc #1 | | | +0 | +1 | +1 | | enetc #2 | | +2 | | | +2 | | enetc #3 | | +3 | | | +3 | | felix p0 | | +0 | | | +4 | | felix p1 | | +1 | | | +5 | | felix p2 | | | | | +6 | | felix p3 | | | | | +7 | | felix p4 | | | | | | | felix p5 | | | | | | +----------+------+------+------+------+------+ An empty cell means, the port is not available and thus doesn't need an ethernet address. Signed-off-by:
Michael Walle <michael@walle.cc> Signed-off-by:
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- Jan 25, 2023
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Alexander Stein authored
This adds an overlay for the supported LVDS display tianma tm070jvhg33. The display timings have to be specified explicitly. Using the typical pixel clock, the LDB clock can not be configured as the 7-fold of that. By setting pixel clock to 74.25 MHz, LDB can be configured to exactly 519.75 MHz. Signed-off-by:
Alexander Stein <alexander.stein@ew.tq-group.com> Signed-off-by:
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Alexander Stein authored
LCDIF2 is directly attached to the LVDS Display Bridge (LDB). Both need the same clock source (VIDEO_PLL1). Signed-off-by:
Richard Leitner <richard.leitner@linux.dev> Tested-by:
Rasmus Villemoes <rasmus.villemoes@prevas.dk> Signed-off-by:
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- Jan 09, 2023
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Peng Fan authored
It is preferred to use syscon per bindind doc Signed-off-by:
Peng Fan <peng.fan@nxp.com> Reviewed-by:
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Peng Fan authored
It is better use syscon for IOMUXC GPR, since it contains various bits for system control Signed-off-by:
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Peng Fan authored
The IOMUX Controller General purpose register group are unique almost per SoC, i.MX8MM is not compatible with i.MX6Q. So correct it. Signed-off-by:
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Peng Fan authored
The IOMUX Controller General purpose register group are unique almost per SoC, i.MX8MQ is not compatible with i.MX6Q. So correct it. Also update name with syscon. Signed-off-by:
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Alexander Stein authored
Use the correct compatible 'nxp,se97b' as it is an SE97BTP chip. While at it, fix the node name according to device tree spec recommendations. The EEPROM is a separate node anyway. Signed-off-by:
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- Jan 01, 2023
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Marek Vasut authored
Add DT nodes for the Hantro VPU found in i.MX8MP SoC. Reviewed-by:
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Adam Ford authored
There is an SPBA bus on AIPS3 which includes ecspi1-3, UART1-3, and Flexcan1-2 according to the TRM. Signed-off-by:
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Marek Vasut authored
Drop "interrupt-names" property, since it is broken. The drivers/dma/mxs-dma.c in Linux kernel does not use it, the property contains duplicate array entries in existing DTs, and even malformed entries (gmpi, should have been gpmi). Get rid of that optional property altogether. Signed-off-by:
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Marek Vasut authored
Drop "interrupt-names" property, since it is broken. The drivers/dma/mxs-dma.c in Linux kernel does not use it, the property contains duplicate array entries in existing DTs, and even malformed entries (gmpi, should have been gpmi). Get rid of that optional property altogether. Signed-off-by:
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Marek Vasut authored
Update the board compatible string such that it matches the YAML DT schema for validation, add the "toradex,verdin-imx8mm-nonwifi" entry. Signed-off-by:
Francesco Dolcini <francesco.dolcini@toradex.com> Signed-off-by:
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Lucas Stach authored
The HSIO blk-ctrl exposes the high performance PLL as a simple clock. Signed-off-by:
Lucas Stach <l.stach@pengutronix.de> Tested-by:
Lukas F. Hartmann <lukas@mntre.com> Signed-off-by:
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Lucas Stach authored
The only difference in PCIe clock configuration between boards is how the PCIe reference clock is generated. The refclock configuration is fully contained in the PCIe PHY node, so the PCIe controller clocks can be set up in the SoC dtsi, as there is no reason for any board to use a different configuration. Signed-off-by:
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Wei Fang authored
The hibernation mode of AR8031 PHY defaults to be enabled after hardware reset. When the cable is unplugged, the PHY will enter hibernation mode after about 10 senconds and the PHY clocks will be stopped to save power. However, due to the design of EQOS, the mac needs the RX_CLK of PHY for software reset to complete. Otherwise the software reset of EQOS will be failed and do not work correctly. The only way is to disable hibernation mode of AR8031 PHY for EQOS, the "qca,disable-hibernation-mode" property is used for this purpose and has already been submitted to the upstream, for more details please refer to the below link: https://lore.kernel.org/netdev/20220818030054.1010660-2-wei.fang@nxp.com/ This issue is easy to reproduce, just unplug the cable and "ifconfig eth0 down", after about 10 senconds, then "ifconfig eth0 up", you will see failure log on the serial port. The log is shown as following: root@imx8dxlevk:~# [34.941970] imx-dwmac 5b050000.ethernet eth0: Link is Down root@imx8dxlevk:~# ifconfig eth0 down [35.437814] imx-dwmac 5b050000.ethernet eth0: FPE workqueue stop [35.507913] imx-dwmac 5b050000.ethernet eth0: PHY [stmmac-1:00] driver [Qualcomm Atheros AR8031/AR8033] (irq=POLL) [35.518613] imx-dwmac 5b050000.ethernet eth0: configuring for phy/rgmii-id link mode root@imx8dxlevk:~# ifconfig eth0 up [71.143044] imx-dwmac 5b050000.ethernet eth0: Register MEM_TYPE_PAGE_POOL RxQ-0 [71.215855] imx-dwmac 5b050000.ethernet eth0: PHY [stmmac-1:00] driver [Qualcomm Atheros AR8031/AR8033] (irq=POLL) [72.230417] imx-dwmac 5b050000.ethernet: Failed to reset the dma [72.236512] imx-dwmac 5b050000.ethernet eth0: stmmac_hw_setup: DMA engine initialization failed [72.245258] imx-dwmac 5b050000.ethernet eth0: __stmmac_open: Hw setup failed SIOCSIFFLAGS: Connection timed out After applying this patch, the software reset of EQOS will be successful. And the log is shown as below. root@imx8dxlevk:~# ifconfig eth0 up [96.114344] imx-dwmac 5b050000.ethernet eth0: Register MEM_TYPE_PAGE_POOL RxQ-0 [96.171466] imx-dwmac 5b050000.ethernet eth0: PHY [stmmac-1:00] driver [Qualcomm Atheros AR8031/AR8033] (irq=POLL) [96.188883] imx-dwmac 5b050000.ethernet eth0: No Safety Features support found [96.196221] imx-dwmac 5b050000.ethernet eth0: IEEE 1588-2008 Advanced Timestamp supported [96.204846] imx-dwmac 5b050000.ethernet eth0: registered PTP clock [96.225558] imx-dwmac 5b050000.ethernet eth0: FPE workqueue start [96.236858] imx-dwmac 5b050000.ethernet eth0: configuring for phy/rgmii-id link mode [96.249358] 8021q: adding VLAN 0 to HW filter on device eth0 Signed-off-by:
Wei Fang <wei.fang@nxp.com> Reviewed-by:
Clark Wang <xiaoning.wang@nxp.com> Signed-off-by:
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Marek Vasut authored
The PMIC on this Variscite SOM and its MX8MM variant lists regulator-name for all LDOs except this LDO5, add the regulator-name property to avoid this omission. Signed-off-by:
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Marek Vasut authored
The "regulator-compatible" property is deprecated and unused, as the match happens on the node name in Linux of_regulator_match() in case the property is not present. Drop the deprecated property from DT. Signed-off-by:
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Marek Vasut authored
The "regulator-compatible" property is deprecated and unused, as the match happens on the node name in Linux of_regulator_match() in case the property is not present. Drop the deprecated property from DT. Signed-off-by:
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Marek Vasut authored
The "regulator-compatible" property is deprecated and unused, as the match happens on the node name in Linux of_regulator_match() in case the property is not present. Drop the deprecated property from DT. Signed-off-by:
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- Dec 31, 2022
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Vladimir Oltean authored
The SMMUv2 driver for MMU-500 reads the ARM_SMMU_GR0_ID0 register at probe time and tries to determine based on the CTTW (Coherent Translation Table Walk) bit whether this feature is supported. Unfortunately, it looks like the SMMU integration in the NXP LS1088A has wrongly tied the cfg_cttw signal to 0, even though the SoC documentation specifies that "The SMMU supports cache coherency for page table walks and DVM transactions for page table cache maintenance operations." Device tree provides the option of overriding the ID register via the dma-coherent property since commit bae2c2d4 ("iommu/arm-smmu: Sort out coherency"), and that's what we do here. Telling struct io_pgtable_cfg that the SMMU page table walks are coherent with the CPU caches brings performance benefits, because it avoids certain operations such as __arm_lpae_sync_pte() for PTE updates. Link: https://lore.kernel.org/linux-iommu/3f3112e4-65ff-105d-8cd7-60495ec9054a@arm.com/ Suggested-by:
Robin Murphy <robin.murphy@arm.com> Signed-off-by:
Vladimir Oltean <vladimir.oltean@nxp.com> Signed-off-by:
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Vladimir Oltean authored
The SMMUv2 driver for MMU-500 reads the ARM_SMMU_GR0_ID0 register at probe time and tries to determine based on the CTTW (Coherent Translation Table Walk) bit whether this feature is supported. Unfortunately, it looks like the SMMU integration in the NXP LS1028A has wrongly tied the cfg_cttw signal to 0, even though the SoC documentation specifies that "The SMMU supports cache coherency for page table walks and DVM transactions for page table cache maintenance operations." Device tree provides the option of overriding the ID register via the dma-coherent property since commit bae2c2d4 ("iommu/arm-smmu: Sort out coherency"), and that's what we do here. Telling struct io_pgtable_cfg that the SMMU page table walks are coherent with the CPU caches brings performance benefits, because it avoids certain operations such as __arm_lpae_sync_pte() for PTE updates. Link: https://lore.kernel.org/linux-iommu/3f3112e4-65ff-105d-8cd7-60495ec9054a@arm.com/ Suggested-by:
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Daniel Scally authored
Add a device tree file describing the Debix Model A board from Polyhex Technology Co. Reviewed-by:
Kieran Bingham <kieran.bingham@ideasonboard.com> Signed-off-by:
Daniel Scally <dan.scally@ideasonboard.com> Reviewed-by:
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Krzysztof Kozlowski authored
By coding style, unit address should not start with 0x. Signed-off-by:
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