- Oct 27, 2020
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Aric Cyr authored
Signed-off-by:
Aric Cyr <aric.cyr@amd.com> Acked-by:
Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Nikola Cornij authored
[Why] Can be used for debug purposes [How] Add max target bpp override field and related handling Signed-off-by:
Nikola Cornij <nikola.cornij@amd.com> Acked-by:
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Anthony Koo authored
| [Header Changes] | - Add GPINT to change timestamping mode for traces Signed-off-by:
Anthony Koo <Anthony.Koo@amd.com> Acked-by:
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Reza Amini authored
[why] So we can track VSC SDP errors from display [how] Define the bit, and use it in driver logic Signed-off-by:
Reza Amini <Reza.Amini@amd.com> Acked-by:
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Taimur Hassan authored
[Why] Underflow counter increases in AGM when performing some mode switches due to timing sync, which is a known hardware issue. [How] Temporarily raise DPG height during timing sync so that underflow is not reported. Signed-off-by:
Taimur Hassan <syed.hassan@amd.com> Acked-by:
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Alvin Lee authored
[Why] If full pstate is not supported, we should set WM set A to 0 to prevent any hangs [How] If pstate is not supported, set watermark set A to 0 Signed-off-by:
Alvin Lee <alvin.lee2@amd.com> Acked-by:
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Eryk Brol authored
This reverts commit c44a22b3 . Reason for revert: Patch introduces performance issues and might cause memory consistency problems with multiple connectors. Signed-off-by:
Eryk Brol <eryk.brol@amd.com> Acked-by:
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Ashley Thomas authored
[Why] Some sink devices wish to have access to the minimum HBlank supported by the ASIC. [How] Make the ASIC minimum HBlank available in Source Device information address 0x340. Signed-off-by:
Ashley Thomas <Ashley.Thomas2@amd.com> Acked-by:
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Dmytro Laktyushkin authored
[WHY & HOW] Enable ODM Combine + Fullscreen MPO on DCN2.1 For lower power consumption in video use cases. Signed-off-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Signed-off-by:
Sung Lee <sung.lee@amd.com> Acked-by:
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Dmytro Laktyushkin authored
[Why&How] Create a separate dcn21_fast_validate_bw function for dcn21. Signed-off-by:
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Sung Lee authored
[WHY] DF PState and Voltage State are coupled such that one cannot be raised without raising the other. This uses more power than is necessary in high bandwidth scenarios. [HOW] Add logic to create a new bounding box state that allows for DF PState to be low while Voltage State is high. Watermarks vlevel calculation logic was also udpated to assume state 1 contains the new optimized state. Signed-off-by:
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Christian König authored
Merge the functionality mostly into amdgpu_vm_bo_update_mapping. This way we can even handle small contiguous system pages without to much extra CPU overhead. v2: fix typo, keep the cursor as it is for now Signed-off-by:
Christian König <christian.koenig@amd.com> Reviewed-by: Madhav Chauhan <madhav.chauhan@amd.com> (v1) Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
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Christian König authored
Ideally this should be a multiple of the VM block size. 2MB should at least fit for Vega/Navi. Signed-off-by:
Madhav Chauhan <madhav.chauhan@amd.com> Reviewed-by:
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Tao Zhou authored
Per PMFW 59.9.0. Signed-off-by:
Tao Zhou <tao.zhou1@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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John Clements authored
loaded fw can be queried from sys fs interface Reviewed-by:
John Clements <john.clements@amd.com> Signed-off-by:
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Xiaomeng Hou authored
enable IP discovery for vangogh. Reviewed-by:
Huang Rui <ray.huang@amd.com> Signed-off-by:
Xiaomeng Hou <Xiaomeng.Hou@amd.com> Signed-off-by:
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- Oct 24, 2020
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David Galiffi authored
[why] get_pixel_clk_frequency_100hz is undefined in clock_source_funcs. [how] set function pointer: ".get_pixel_clk_frequency_100hz = get_pixel_clk_frequency_100hz" Signed-off-by:
David Galiffi <David.Galiffi@amd.com> Reviewed-by:
Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Acked-by:
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xinhui pan authored
Size is page count here. Reviewed-by:
xinhui pan <xinhui.pan@amd.com> Signed-off-by:
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Mauro Carvalho Chehab authored
dm_comressor_info -> dm_compressor_info The kernel-doc markup is right, but the struct itself and their references contain a typo. Signed-off-by:
Mauro Carvalho Chehab <mchehab+huawei@kernel.org> Signed-off-by:
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Mauro Carvalho Chehab authored
Some functions have different names between their prototypes and the kernel-doc markup. Acked-by:
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Mauro Carvalho Chehab authored
A kernel-doc markup can't be mixed with a random comment, as it causes parsing problems. While here, change an invalid kernel-doc markup into a common comment. Acked-by:
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Harish Kasiviswanathan authored
Workaround to fix the soft hang observed in certain compute applications. Acked-by:
Evan Quan <evan.quan@amd.com> Reviewed-by:
Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com> Signed-off-by:
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Madhav Chauhan authored
2MB area is reserved at top inside VM. Suggested-by:
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Bhawanpreet Lakha authored
Enable Memory Access at Last Level (MALL) feature for display. v2: squash in 64 bit division fixes Signed-off-by:
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Likun Gao authored
Enable Memory Access at Last Level (MALL) feature for sienna_cichlid. v2: drop module option. We need to add UAPI so userspace can request MALL per buffer. Reviewed-by:
Likun Gao <Likun.Gao@amd.com> Reviewed-by:
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Alex Deucher authored
This adds the NOALLOC registers. Signed-off-by: -
Tom Rix authored
A break is not needed if it is preceded by a return or break Reviewed-by:
Harry Wentland <harry.wentland@amd.com> Acked-by:
Tom Rix <trix@redhat.com> Signed-off-by:
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Tianci.Yin authored
Reviewed-by:
Guchun Chen <guchun.chen@amd.com> Signed-off-by:
Tianci.Yin <tianci.yin@amd.com> Signed-off-by:
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Tianci.Yin authored
The blockchain SKU has no display and video support, remove them. Reviewed-by:
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Likun Gao authored
Skip disabled sa to correct the cu_info and active_rbs for sienna cichlid. Signed-off-by:
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Kenneth Feng authored
if it's fine-grained clock dpm, remove the average clock value and reflects the real clock. Signed-off-by:
Kenneth Feng <kenneth.feng@amd.com> Reviewed-by:
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- Oct 22, 2020
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Mauro Carvalho Chehab authored
Running "make htmldocs: produce lots of warnings on those files: ./drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c:177: warning: Excess function parameter 'man' description in 'amdgpu_vram_mgr_init' ./drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c:177: warning: Excess function parameter 'p_size' description in 'amdgpu_vram_mgr_init' ./drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c:211: warning: Excess function parameter 'man' description in 'amdgpu_vram_mgr_fini' ./drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c:177: warning: Excess function parameter 'man' description in 'amdgpu_vram_mgr_init' ./drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c:177: warning: Excess function parameter 'p_size' description in 'amdgpu_vram_mgr_init' ./drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c:211: warning: Excess function parameter 'man' description in 'amdgpu_vram_mgr_fini' ./drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c:177: warning: Excess function parameter 'man' description in 'amdgpu_vram_mgr_init' ./drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c:177: warning: Excess function parameter 'p_size' description in 'amdgpu_vram_mgr_init' ./drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c:211: warning: Excess function parameter 'man' description in 'amdgpu_vram_mgr_fini' ./drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c:177: warning: Excess function parameter 'man' description in 'amdgpu_vram_mgr_init' ./drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c:177: warning: Excess function parameter 'p_size' description in 'amdgpu_vram_mgr_init' ./drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c:211: warning: Excess function parameter 'man' description in 'amdgpu_vram_mgr_fini' ./drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c:90: warning: Excess function parameter 'man' description in 'amdgpu_gtt_mgr_init' ./drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c:90: warning: Excess function parameter 'p_size' description in 'amdgpu_gtt_mgr_init' ./drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c:134: warning: Excess function parameter 'man' description in 'amdgpu_gtt_mgr_fini' ./drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c:90: warning: Excess function parameter 'man' description in 'amdgpu_gtt_mgr_init' ./drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c:90: warning: Excess function parameter 'p_size' description in 'amdgpu_gtt_mgr_init' ./drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c:134: warning: Excess function parameter 'man' description in 'amdgpu_gtt_mgr_fini' ./drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:675: warning: Excess function parameter 'dev' description in 'amdgpu_device_asic_init' ./drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:675: warning: Excess function parameter 'dev' description in 'amdgpu_device_asic_init' ./drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:675: warning: Excess function parameter 'dev' description in 'amdgpu_device_asic_init' ./drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:675: warning: Excess function parameter 'dev' description in 'amdgpu_device_asic_init' They're related to the repacement of some parameters by adev, and due to a few renamed parameters. While here, uniform the name of the parameter for it to be the same on all functions using a pointer to struct amdgpu_device. Update the kernel-doc documentation accordingly. Signed-off-by:
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Sumera Priyadarsini authored
Return statements for functions returning bool should use truth and false instead of 1 and 0 respectively. Modify cik_event_interrupt.c to return false instead of 0. Issue found with Coccinelle. Signed-off-by:
Sumera Priyadarsini <sylphrenadin@gmail.com> Signed-off-by:
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Yifan Zhang authored
[Why] Screen corruption on Navi10 card [How] Set system context in DCN only on Renoir Tested-by:
Matt Coffin <mcoffin13@gmail.com> Acked-by:
Yifan Zhang <yifan1.zhang@amd.com> Reviewed-by:
Roman Li <Roman.Li@amd.com> Signed-off-by:
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Kenneth Feng authored
fclk value is missing in pp_dpm_fclk. add this to correctly show the current value. Signed-off-by:
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John Clements authored
This reverts commit 265c280a . Reviewed-by:
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Kenneth Feng authored
fix the wrong fan speed in fan1_input when the fan control mode is manual. the fan speed value is not correct when we set manual mode to fan1_enalbe - 1. since the fan speed in the metrics table always reflects the real fan speed,we can fetch the fan speed for both auto and manual mode. Signed-off-by:
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Bas Nieuwenhuizen authored
As far a I can tell uses a variant of DCN3xx which uses num_pkrs. If we do not initialize the variable we will set the register field to ilog2(0) = -1, though the mask will reduce that to 7. Pretty sure 7 is not the value we want here. Signed-off-by:
Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Reviewed-by:
Marek Olšák <marek.olsak@amd.com> Reviewed-and-Tested-by:
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Likun Gao authored
Update driver if file for sienna cichlid. Signed-off-by:
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Likun Gao authored
Fix the function used for sienna cichlid to get correct PCIE information by pp_dpm_pcie. Signed-off-by:
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