- Mar 16, 2022
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Charlene Liu authored
[why] DCN31 has this in zstate save/restore sequence. need for non_zstate supported ASIC [how] add this PANEL_PWRSEQ_REF_DIV2 to existing panel_cntl_hw_init structure. Reviewed-by:
Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by:
Agustin Gutierrez <agustin.gutierrez@amd.com> Signed-off-by:
Charlene Liu <Charlene.Liu@amd.com> Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Becle Lee authored
[Why] Underflow occurred while hubp ret pipe read is idle and the second pipe is powered up and added. Flickering and underflow are only observed on Pollock. [How] Check the hubp ret pipe read prior to unlock pipes. Reviewed-by:
Hersen Wu <hersenxs.wu@amd.com> Reviewed-by:
Aric Cyr <Aric.Cyr@amd.com> Acked-by:
Becle Lee <becle.lee@amd.com> Tested-by:
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Jing Zhou authored
[Why & How] Add null pointer filter for logical integrity. Reviewed-by:
Jing Zhou <Jing.Zhou@amd.com> Tested-by:
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Wayne Lin authored
[Why] In dp_get_lane_status_and_lane_adjust(), we call core_link_read_dpcd() to get lane status but we ignore the return value of the function. If there is problem with AUX and we eventually can only get partial data from monitor, we might misuse the data to jude the link training result. Which could have us trapped in the dc_link_dp_perform_link_training() since we thought that we can still give a try on another link setting. [How] In dp_get_lane_status_and_lane_adjust(), take return value of core_link_read_dpcd() into account. If we fail to read all requested data, we treat lanes status as previous one and repeat LT steps again. Reviewed-by:
Wenjing Liu <Wenjing.Liu@amd.com> Acked-by:
Wayne Lin <Wayne.Lin@amd.com> Tested-by:
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Dale Zhao authored
[Why] We must support a new type of partial edid return in the future [How] Add interface and case hander for partial edid Reviewed-by:
Dale Zhao <dale.zhao@amd.com> Tested-by:
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Eric Yang authored
[Why] Currently Z10 save/restore only covers 1 plane case. If we enter Z10 with 2 planes enabled, 1 of the 2 planes will not be restored. causing black screen. [How] Disable Zstate when more than 1 plane is enabled. Right now Z9 enable but Z10 disable is not a supported config, so we disable both. Reviewed-by:
Nevenko Stupar <Nevenko.Stupar@amd.com> Acked-by:
Eric Yang <Eric.Yang2@amd.com> Tested-by:
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Jing Zhou authored
[Why] Crash caused by a ddc update failure [How] Update engine ddc before release engine. Reviewed-by:
Wyatt Wood <Wyatt.Wood@amd.com> Reviewed-by:
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Wayne Lin authored
[Why & How] 1. To leverage and simplify the igt tool. Change the value of retrain when calling preferred training settings. Now, writing value to link settings triggers link training immediately. 2. Add dc lock when triggering link training in edp_ilr_write() Reviewed-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Acked-by:
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Leo (Hanghong) Ma authored
[Why] We need a helper function in dc to grab the pipe from the stream context. [How] Add it. Reviewed-by:
Martin Leung <Martin.Leung@amd.com> Acked-by:
Leo (Hanghong) Ma <hanghong.ma@amd.com> Tested-by:
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JinZe.Xu authored
[How] 1. Search OEM I2C info from BIOS and compare with input parameter. 2. If BIOS doesn't record it, just try to read one byte. Reviewed-by:
JinZe.Xu <JinZe.Xu@amd.com> Tested-by:
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Philip Yang authored
amdgpu_detect_virtualization reads register, amdgpu_device_rreg access adev->reset_domain->sem if kernel defined CONFIG_LOCKDEP, below is the random boot hang backtrace on Vega10. It may get random NULL pointer access backtrace if amdgpu_sriov_runtime is true too. Move amdgpu_reset_create_reset_domain before calling to RREG32. BUG: kernel NULL pointer dereference, address: #PF: supervisor read access in kernel mode #PF: error_code(0x0000) - not-present page PGD 0 P4D 0 Oops: 0000 [#1] PREEMPT SMP NOPTI Workqueue: events work_for_cpu_fn RIP: 0010:down_read_trylock+0x13/0xf0 Call Trace: <TASK> amdgpu_device_skip_hw_access+0x38/0x80 [amdgpu] amdgpu_device_rreg+0x1b/0x170 [amdgpu] amdgpu_detect_virtualization+0x73/0x100 [amdgpu] amdgpu_device_init.cold.60+0xbe/0x16b1 [amdgpu] ? pci_bus_read_config_word+0x43/0x70 amdgpu_driver_load_kms+0x15/0x120 [amdgpu] amdgpu_pci_probe+0x1a1/0x3a0 [amdgpu] Fixes: d0fb18b5 ("drm/amdgpu: Move reset sem into reset_domain") Signed-off-by:
Philip Yang <Philip.Yang@amd.com> Reviewed-by:
Andrey Grodzovsky <andrey.grodzovsky@amd.com> Signed-off-by:
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Tianci.Yin authored
[why] CP hangs in igt reloading test on renoir, more precisely, hangs on the second time insmod. [how] mode2 reset can make it recover, and mode2 reset only effects gfx core, dcn and the screen will not be impacted. Acked-by:
Tianci.Yin <tianci.yin@amd.com> Signed-off-by:
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Alex Deucher authored
We don't support runtime pm on APUs. They support more dynamic power savings using clock and powergating. Reviewed-by:
Mario Limonciello <mario.limonciello@amd.com> Tested-by:
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Stanley.Yang authored
Signed-off-by:
Stanley.Yang <Stanley.Yang@amd.com> Reviewed-by:
Evan Quan <evan.quan@amd.com> Signed-off-by:
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Hawking Zhang authored
xgmi_ras is only initialized when host to GPU interface is PCIE. in such case, xgmi23 is disabled and protected by security firmware. Host access will results to security violation Signed-off-by:
Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by:
Tao Zhou <tao.zhou1@amd.com> Signed-off-by:
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Jonathan Kim authored
VFs must also distinguish whether or not the TA supports full duplex or half duplex link records in order to report the correct xGMI topology. Signed-off-by:
Jonathan Kim <jonathan.kim@amd.com> Reviewed-by:
Shaoyun Liu <shaoyun.liu@amd.com> Signed-off-by:
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Alex Deucher authored
Enable scatter/gather display for DCN 3.1.6. Reviewed-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
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Nicholas Kazlauskas authored
[Why] To debug when p-state is being blocked and avoid PMFW hangs when it does occur. [How] Re-use the DCN10 hardware sequencer by adding a new interface for verifying p-state high on the hubbub. The interface is mostly the same as the DCN10 interface, but the bit definitions have changed for the debug bus. Signed-off-by:
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David Yat Sin authored
Export dmabuf handles for GTT BOs so that their contents can be accessed using SDMA during checkpoint/restore. v2: Squash in fix from David to set dmabuf handle to invalid for BOs that cannot be accessed using SDMA during checkpoint/restore. Signed-off-by:
David Yat Sin <david.yatsin@amd.com> Reviewed-by : Rajneesh Bhardwaj <rajneesh.bhardwaj@amd.com> Signed-off-by:
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David Yat Sin authored
Refactor CRIU restore BO to reduce identation. Signed-off-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
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David Yat Sin authored
When the process is getting restored, the queues are not mapped yet, so there is no VMID assigned for this process and no TLBs to flush. Signed-off-by:
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Tianci.Yin authored
[why] The DP KVM failed to light up, since the lttpr_mode is not reset to default value when failed to read LTTPR capabilities, and the variable max_link_rate retains a initial value zero, this cause variable link_rate be assigned to an error value zero, consquently pixel_clock get wrong value zero, and kvm can't light up. [how] Reset lttpr_mode to default value when failed to read LTTPR capabilities, so that the link_rate fallbacks to the minimum rate that supported by link encoder and sink. Reviewed-by:
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Lijo Lazar authored
When PMFW is really busy, it will respond with 0xFC. However, it doesn't change the response register state when it becomes free. Driver should retry and proceed to send message if the response status is 0xFC. Signed-off-by:
Lijo Lazar <lijo.lazar@amd.com> Reviewed-by:
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Stanley.Yang authored
It should notice SMU to update bad channel info when detected uncorrectable error in UMC block Signed-off-by:
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Stanley.Yang authored
support message SMU update bad channel info to update HBM bad channel info in OOB table Signed-off-by:
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Melissa Wen authored
FPU operations in dcn10 was already moved to dml folder via calcs code. However, dcn1_0_ip and dcn_1_0_soc with FPU componentd remains on dcn10. Following previous changes to isolate FPU, this patch creates dcn10_fpu files to isolate FPU-specific code and moves those structs to it. Signed-off-by:
Melissa Wen <mwen@igalia.com> Acked-by:
Alan Liu <HaoPing.Liu@amd.com> Tested-by:
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Melissa Wen authored
dml/dcn20_fpu file centralizes all DCN2x functions that require FPU access. Therefore, this patch moves FPU-related code from dcn21 to dcn20_fpu. These include: - dcn21_populate_dml_pipes_from_context() - dcn21_validate_bandwidth_fp() and related: - dcn21_calculate_wm(), - patch_bounding_box(), - calculate_wm_set_for_vlevel() - renaming update_bw_bounding_box() to dcn21_update_bw_bounding_box(), move to dcn20_fpu with related static function construct_low_pstate_lvl() Also, make dcn21_fast_validate_bw() public in dcn21_resource as it is called by dcn21_validate_bandwidth_fp() now in dcn20_fpu. Reuse dcn20_fpu_adjust_dppclk() in dcn21_fast_validate_bw() as it isolates the same FPU operation. Include dchubbub.h as it is required in dcn21_populate_dml_pipes_from_context() Signed-off-by:
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Melissa Wen authored
Move parts of dcn20 code that uses FPU to dml folder. It aims to isolate FPU operations as described by series: drm/amd/display: Introduce FPU directory inside DC https://patchwork.freedesktop.org/series/93042/ This patch moves the following functions from dcn20_resource to dml/dcn20_fpu and calls of public functions in dcn20_resource are wrapped by DC_FP_START/END(): - void dcn20_populate_dml_writeback_from_context - static bool is_dtbclk_required() - static enum dcn_zstate_support_state() - void dcn20_calculate_dlg_params() - static void swizzle_to_dml_params() - int dcn20_populate_dml_pipes_from_context() - void dcn20_calculate_wm() - void dcn20_cap_soc_clocks() - void dcn20_update_bounding_box() - void dcn20_patch_bounding_box() - bool dcn20_validate_bandwidth_fp() This movement also affects dcn21/30/31, as dcn20_calculate_dlg_params() is used by them. For this reason, I included dcn20_fpu headers in dcn20_resource headers to make dcn20_calculate_dlg_params() visible to dcn21/30/31. Three new functions are created to isolate well-delimited FPU operations: - void dcn20_fpu_set_wb_arb_params(): set cli_watermark, pstate_watermark and time_per_pixel from wb_arb_params (struct mcif_arb_params), since those uses FPU operations on double types: WritebackUrgentWatermark, WritebackDRAMClockChangeWatermark, '16.0'. - void dcn20_fpu_set_wm_ranges(): set min_fill_clk_mhz and max_fill_clk_mhz involves FPU calcs on dram_speed_mts (double type); - void dcn20_fpu_adjust_dppclk(): adjust operation on RequiredDPPCLK that is a double. Signed-off-by:
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Leo Li authored
[Why] On LNX, TO_CLK_MGR_INTERNAL() only works to get clk_mgr_internal from a given clk_mgr. In clk_mgr_dcn316 struct, the clk_mgr_internal is already a memeber by the alias 'base' [How] Use &clk_mgr->base instead. Reviewed-by:
Leo Li <sunpeng.li@amd.com> Tested-by:
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Nicholas Kazlauskas authored
[Why] The issue only occurs during the GPU reset code path. We first backup the current state prior to commiting 0 streams internally from DM to DC. This state backup contains valid link encoder assignments. DC will clear the link encoder assignments as part of current state (but not the backup, since it was a copied before the commit) and free the extra stream reference it held. DC requires that the link encoder assignments remain cleared/invalid prior to commiting. Since the backup still has valid assignments we call the interface post reset to clear them. This routine also releases the extra reference that the link encoder interface held - resulting in a double free (and eventually a NULL pointer dereference). [How] We'll have to do a full DC commit anyway after GPU reset because the stream count previously went to 0. We don't need to retain the assignment that we had backed up, so just copy off of the now clean current state assignment after the reset has occcurred with the new link_enc_cfg_copy() interface. Fixes: 6d63fcc2 ("drm/amd/display: Reset link encoder assignments for GPU reset") Reviewed-by:
Jimmy Kizito <Jimmy.Kizito@amd.com> Acked-by:
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Chris Park authored
[Why] Virtualization enters blue screen of death (BSoD) due to NULL res_pool object when accessing DSC encoder capability. [How] Add NULL check to avoid blue screen of death. Reviewed-by:
Chris Park <Chris.Park@amd.com> Tested-by:
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Aric Cyr authored
drm/amd/display: 3.2.176 This version brings along following fixes: - move FPU operations from dcn21 to dml/dcn20 folder - move FPU-related code from dcn20 to dml folder - Fix compile error from TO_CLK_MGR_INTERNAL - Fix double free during GPU reset on DC streams - Add NULL check - [FW Promotion] Release 0.0.107.0 - enable dcn315/316 s0i2 support - handle DP2.0 RX with UHBR20 but not UHBR13.5 support - disable HPD SW timer for passive dongle type 1 only - add gamut coefficient set A and B - merge two duplicated clock_source_create - Add link dp trace support - move FPU associated DCN303 code to DML folder - Release AUX engine after failed acquire - Add minimal pipe split transition state - Clean up fixed VS PHY test w/a function - fix the clock source contruct for dcn315 - cleaning up smu_if to add future flexibility - fix deep color ratio - add debug option to bypass ssinfo from bios for dcn315 Acked-by: -
Anthony Koo authored
Reviewed-by:
Anthony Koo <Anthony.Koo@amd.com> Tested-by:
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Charlene Liu authored
[why] enable the support in driver, let the control by CMOS Reviewed-by:
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Wenjing Liu authored
[why] DP2.0 defines DP2.0 RX capability using bit maps. This means there is a corner case the DP2.0 RX can declare UHBR20 capability but not UHBR13.5 support. In this case we should skip UHBR13.5 selection and continue to our next option in decide liink settings. Reviewed-by:
George Shen <George.Shen@amd.com> Acked-by:
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Sung Joon Kim authored
[why] Need to provide this workaround only for type 1 passive dongle [how] Detect if dongle is type 1 or 2. And use it to determine if w/a is needed. Reviewed-by:
Sung Joon Kim <sungjoon.kim@amd.com> Tested-by:
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Jingwen Zhu authored
[Why] Screen shake on DCN3 night light SDR BR3. [How] Change the logic to use double buffer reisgter on gamut settings. Reviewed-by:
Krunoslav Kovac <Krunoslav.Kovac@amd.com> Acked-by:
Jingwen Zhu <jingwen.zhu@amd.com> Tested-by:
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Charlene Liu authored
[why] dcn31x could use dcn31 sepcific which contains deep_color_ratio for dmub Reviewed-by:
Hansen Dsouza <hansen.dsouza@amd.com> Reviewed-by:
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Leo (Hanghong) Ma authored
[Why] It is nice to have link training and link loss status logging in our trace, and this patch add the all necessary accessors in dc side. [How] 1. Define dp_trace struct and create new file link_dp_trace.c and link_dp_trace.h; 2. Add dp link training status update in dc_link_dp.c; Reviewed-by:
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Jasdeep Dhillon authored
[Why & How] As part of the FPU isolation work documented in https://patchwork.freedesktop.org/series/93042/ , isolate code that uses FPU in DCN303 to DML, where all FPU code should locate. Co-authored-by:
Jasdeep Dhillon <jasdeep.dhillon@amd.com> Reviewed-by:
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