- Jan 06, 2020
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Vinod Koul authored
Add the core UFS reset for sdm845 Signed-off-by:
Vinod Koul <vkoul@kernel.org> Link: https://lore.kernel.org/r/20200106070826.147064-4-vkoul@kernel.org Signed-off-by:
Bjorn Andersson <bjorn.andersson@linaro.org>
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Vinod Koul authored
UFS phy register space size is 0x1c0. so update it Reported-by:
Can Guo <cang@codeaurora.org> Signed-off-by:
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Vinod Koul authored
Add the reset-gpio for UFS for sm8150-mtp. Signed-off-by:
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- Jan 05, 2020
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Niklas Cassel authored
Add CPR and populate OPP table. Co-developed-by:
Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org> Signed-off-by:
Niklas Cassel <niklas.cassel@linaro.org> Reviewed-by:
Ulf Hansson <ulf.hansson@linaro.org> Link: https://lore.kernel.org/r/20191129213917.1301110-4-niklas.cassel@linaro.org Signed-off-by:
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Jorge Ramirez-Ortiz authored
Support dynamic voltage and frequency scaling on qcs404. CPUFreq will soon be superseded by Core Power Reduction (CPR, a form of Adaptive Voltage Scaling found on some Qualcomm SoCs like the qcs404). Due to the CPR upstreaming already being in progress - and some commits already merged - the following commit will need to be reverted to enable CPUFreq support Author: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org> Date: Thu Jul 25 12:41:36 2019 +0200 cpufreq: Add qcs404 to cpufreq-dt-platdev blacklist Co-developed-by: -
Jorge Ramirez-Ortiz authored
Specify the clocks that feed the APCS mux/divider instead of using default hardcoded values in the source code. Co-developed-by:
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Jorge Ramirez-Ortiz authored
The high frequency pll functionality is required to enable CPU frequency scaling operation. Co-developed-by:
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Jorge Ramirez-Ortiz authored
Specify the clocks that feed the APCS mux/divider instead of using default hardcoded values in the source code. The driver still supports the previous bindings; however with this update it we allow the msm8916 to access the parent clock names required by the driver operation using the device tree node. Signed-off-by:
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Sibi Sankar authored
Add the DT node for the rpmhpd power controller on SC7180 SoCs. Reviewed-by:
Rajendra Nayak <rnayak@codeaurora.org> Reviewed-by:
Stephen Boyd <swboyd@chromium.org> Signed-off-by:
Sibi Sankar <sibis@codeaurora.org> Link: https://lore.kernel.org/r/20191220064823.6115-3-sibis@codeaurora.org Signed-off-by:
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- Jan 04, 2020
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AngeloGioacchino Del Regno authored
Add the SPMI regulator node in the PM8004 LSID5 (as there is where it resides basically 99% of the times) and set the nodes to be disabled by default, as not all boards have both or one of the lsids specified in this generic pm8004 DT. While at it, also add nice phandles to the lsids specified in this DT to allow configuration in specific board dts in a more human readable fashion. Signed-off-by:
AngeloGioacchino Del Regno <kholk11@gmail.com> Link: https://lore.kernel.org/r/20191031111645.34777-3-kholk11@gmail.com Signed-off-by:
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- Dec 29, 2019
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Amit Kucheria authored
Register critical interrupts for each of the two tsens controllers Signed-off-by:
Amit Kucheria <amit.kucheria@linaro.org> Link: https://lore.kernel.org/r/3ef309a98ca6445c1982ec3ff1a70db39b18f415.1575349416.git.amit.kucheria@linaro.org Signed-off-by:
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Amit Kucheria authored
Register critical interrupts for each of the two tsens controllers Signed-off-by:
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- Dec 27, 2019
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Bjorn Andersson authored
The redistributable firmware should work on any engineering device, so lets push this to qcom/sdm845, rather than qcom/db845c. Also specify the path for the modem firmware. Reviewed-by:
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Bjorn Andersson authored
Introduce a base dts for the Inforce 6640 Single Board Computer. This initial commit boots to console on the uart and provides UFS and SD card storage support. Acked-by:
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Bjorn Andersson authored
Update the regulator names in db820c.dtsi to use the names from the schematics, instead of the made up genric names. Acked-by:
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Bjorn Andersson authored
Sort all the nodes by unit address, then name. Acked-by:
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Bjorn Andersson authored
Pad all addresses in msm8996.dtsi to 8 digits, in order to make it easier to ensure ordering when adding new nodes. Acked-by:
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Bjorn Andersson authored
Rather than scattering pinctrl definitions in various files, merge the nodes into db820c.dtsi to make it easier to navigate. Acked-by:
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Bjorn Andersson authored
Sort all nodes in db820c.dtsi based on address, then name. Acked-by:
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Bjorn Andersson authored
Prior refactoring have left a few root nodes scattered throughout db820c.dtsi, group these at the top of the file. Acked-by:
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Bjorn Andersson authored
As the definition of available PMICs and the names of their outputs are board specifc move this to db820c.dtsi Acked-by:
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Bjorn Andersson authored
Supplies for the various components in the SoC depends on board layout, so move the supply definitions to db820c.dtsi instead of carrying them in the platform dtsi. Acked-by:
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Bjorn Andersson authored
Instead of mimicing the structure of the platform, reference nodes by their label in apq8096-db820c.dtsi. Add labels in msm8996.dtsi where necessary. Acked-by:
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Bjorn Andersson authored
The USB id pins and wlan regulator are not platform devices, so move them out of /soc Acked-by:
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- Dec 22, 2019
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Bjorn Andersson authored
The WiFi firmware used on db845c implements the 8bit host-capability message, so enable the quirk for this. Reviewed-by:
Jeffrey Hugo <jeffrey.l.hugo@gmail.com> Signed-off-by:
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Douglas Anderson authored
This is just like commit ac00546a ("arm64: dts: qcom: sc7180: Rename gic-its node to msi-controller") but for sdm845. This fixes all arm64/qcom device trees that I could find. Reviewed-by:
Douglas Anderson <dianders@chromium.org> Link: https://lore.kernel.org/r/20191216222021.1.I684f124a05a1c3f0b113c8d06d5f9da5d69b801e@changeid Signed-off-by:
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- Dec 21, 2019
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Sibi Sankar authored
This patch adds ADSP, MPSS and SLPI nodes for MSM8998 SoCs. Signed-off-by:
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Sibi Sankar authored
Update existing and add missing regions to the reserved memory map, as described in version 7.1 Signed-off-by:
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- Dec 20, 2019
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Sibi Sankar authored
Add scm, smem, smp2p, aoss-qmp, aoss-cc and pdc-global device nodes to SC7180 SoCs. Signed-off-by:
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Sibi Sankar authored
Add cpufreq HW device node to scale 4-Silver/3-Gold/1-Gold+ cores on SM8150 SoCs. Signed-off-by:
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Sai Prakash Ranjan authored
Update the compatible for QCS404 watchdog timer with proper SoC specific compatible. Signed-off-by:
Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> Link: https://lore.kernel.org/r/757995875cc12d3f5a8f5fd5659b04653950970a.1576211720.git.saiprakash.ranjan@codeaurora.org Signed-off-by:
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- Dec 19, 2019
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Douglas Anderson authored
Commit f4a73f5e ("pinctrl: qcom: sc7180: Add new qup functions") has landed which means that we absolutely need to use the proper names for the pinmuxing for I2C/UART numbers 2, 4, 7, and 9. Let's do it. For reference: - If you get only one of this commit and the pinctrl commit then none of I2C/UART 2, 4, 7, and 9 will work. - If you get neither of these commits then I2C 2, 4, 7, and 9 will work but not UART. ...but despite the above it should be fine for this commit to land in the Qualcomm tree because sc7180.dtsi only exists there (it hasn't made it to mainline). Reviewed-by:
Matthias Kaehlcke <mka@chromium.org> Reviewed-by:
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- Dec 18, 2019
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Jeffrey Hugo authored
The pm8005_s1 is VDD_GFX, and needs to be on to enable the GPU. This should be hooked up to the GPU CPR, but we don't have support for that yet, so until then, just turn on the regulator and keep it on so that we can focus on basic GPU bringup. Signed-off-by:
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Maulik Shah authored
Specify wakeup parent irqchip for sc7180 TLMM. Reviewed-by:
Lina Iyer <ilina@codeaurora.org> Reviewed-by:
Maulik Shah <mkshah@codeaurora.org> Link: https://lore.kernel.org/r/1572419178-5750-3-git-send-email-mkshah@codeaurora.org Signed-off-by:
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Sibi Sankar authored
Add ADSP, CDSP, MPSS and SLPI device tree nodes for SM8150 SoC. Tested-by:
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Matthias Kaehlcke authored
The SC7180 device tree nodes should be ordered by address. Re-shuffle some nodes which currently don't follow this convention. Since we are already moving it add a missing leading zero to the address in the 'reg' property of the 'interrupt-controller@b220000' node. Signed-off-by:
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Jeffrey Hugo authored
It turns out that the wcn3990 can float the gpio lines during bootup, etc which will result in the uart core thinking there is incoming data. This results in the bluetooth stack getting garbage. By applying a bias to match what wcn3990 would drive, the issue is corrected. Signed-off-by:
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- Dec 17, 2019
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Stephen Boyd authored
Add the cr50 device to the spi controller it is attached to. This enables /dev/tpm0 and some login things on Cheza. Reviewed-by:
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Sibi Sankar authored
Add the SMP2P nodes for the remoteproc states for ADSP, CDSP, MPSS and SLPI remoteprocs. Signed-off-by:
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- Dec 13, 2019
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Douglas Anderson authored
The bindings for the QMP PHY are truly strange. I believe (?) that they may have originated because with PCIe each lane is treated as a different PHY and the same PHY driver is used for a whole bunch of things (incluidng PCIe). In any case, now that we have "make dtbs_check", we find that having the outer node named "phy" triggers the "schemas/phy/phy-provider.yaml" schema, yelling about: phy@88e9000: '#phy-cells' is a required property Let's call the outer node the "phy-wrapper" and the inner node the "phy" to make dtbs_check happy. Reviewed-by:
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