- Jul 20, 2020
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Fabio Estevam authored
imx6q-tbs2910 has an Atheros AR8035 Ethernet PHY at address 4. The AR8035 provides a 125MHz clock to the ENET_REF_CLK i.MX6 pin. Improve the Ethernet representation by adding an mdio node with such information. This fixes an Ethernet regression in U-Boot as U-Boot AR803X driver now expects the 'qca,clk-out-frequency' property to be passed via device tree. Signed-off-by:
Fabio Estevam <festevam@gmail.com> Reviewed-by:
Soeren Moch <smoch@web.de> Tested-by:
Shawn Guo <shawnguo@kernel.org>
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Fabio Estevam authored
According to the AR8031 datasheet: "When using crystal, clock is generated internally after the power is stable. In order to get reliable power-on-reset, it is recommended to keep asserting the reset low signal long enough (10 ms) to ensure the clock is stable and clock-to-reset (1 ms) requirement is satisfied." Pass the 'reset-assert-us' property to describe such requirement. While at it, use the 'reset-gpios' property inside the the mdio node instead of the deprecated usage of 'phy-reset-gpios'. Signed-off-by:
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Fabio Estevam authored
imx6qdl-sabresd has an Atheros AR8031 Ethernet PHY at address 1. The AR8031 provides a 125MHz clock to the ENET_REF_CLK i.MX6 pin. Improve the Ethernet representation by adding an mdio node with such information. An advantage of adding the mdio node is that the AR8031 initialization code in the mx6sabresd board file in U-Boot can totally be removed. Signed-off-by:
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Tim Harvey authored
Add Gateworks System Controller support to Gateworks Ventana boards: - add dt bindings for GSC mfd driver and hwmon driver for ADC's and fan controllers. - add dt bindings for gpio-keys driver for push-button and interrupt events Signed-off-by:
Tim Harvey <tharvey@gateworks.com> Signed-off-by:
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- Jul 13, 2020
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Parthiban Nallathambi authored
Add support for the MYiR imx6ULL based single board computer equipped with on board 256MB NAND & RAM. The board also provides expansion header for expansion board, but this commit adds only support for SBC. Signed-off-by:
Parthiban Nallathambi <parthiban@linumiz.com> Signed-off-by:
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Chris Healy authored
Add I2C child node for switch watchdog present on SPB4 Signed-off-by:
Chris Healy <cphealy@gmail.com> Signed-off-by:
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Philippe Schenker authored
This is not necessary without a pinctrl-0 statement. Remove this orphan. Signed-off-by:
Philippe Schenker <philippe.schenker@toradex.com> Reviewed-by:
Oleksandr Suvorov <oleksandr.suvorov@toradex.com> Signed-off-by:
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Uwe Kleine-König authored
The imx-pwm driver supports 3 cells and this is the more flexible setting. So use it by default and overwrite it back to two for the files that reference the PWMs with just 2 cells to minimize changes. This allows to drop explicit setting to 3 cells for the boards that already depend on this. The boards that are now using 2 cells explicitly can be converted to 3 individually. Signed-off-by:
Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by:
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Andrew Lunn authored
The SFF soldered onto the board expect the ports to use 1000BaseX. It makes no sense to have the ports set to SGMII, since they don't even support that mode. Signed-off-by:
Andrew Lunn <andrew@lunn.ch> Signed-off-by:
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Chris Healy authored
The SFF soldered onto the board expects the port to use 1000BaseX. It makes no sense to have the port set to SGMII, since it doesn't even support that mode. Signed-off-by:
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Chris Healy authored
Update MDIO configuration with ZII devices to fully utilize MDIO endpoint capabilities. All devices support 12.5MHz clock and don't require MDIO preable. Signed-off-by:
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Andrey Smirnov authored
Add node for CAAM device in NXP Vybrid SoC. Signed-off-by:
Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by:
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Richard Zhu authored
Enable SATA on iMX6QP SABRESD board. Signed-off-by:
Richard Zhu <hongxing.zhu@nxp.com> Reviewed-by:
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Richard Zhu authored
Enable SATA on iMX6QP SABREAUTO board. Signed-off-by:
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Oleksij Rempel authored
Protonic RVT is an internal development platform for a wireless ISObus Virtual Terminal based on COTS tablets, and the predecessor of the WD2 platform. Reviewed-by:
Rob Herring <robh@kernel.org> Signed-off-by:
David Jander <david@protonic.nl> Signed-off-by:
Oleksij Rempel <o.rempel@pengutronix.de> Signed-off-by:
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Oleksij Rempel authored
The Protonic VT7 is a mid-class ISObus Virtual Terminal with a 7 inch touchscreen display. Reviewed-by:
Robin van der Gracht <robin@protonic.nl> Signed-off-by:
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Oleksij Rempel authored
Add support for the Protonic WD2 board, which is an internal development platform for low-cost agricultural Virtual Terminals based on COTS tablets and web applications. It inherits from the PRTI6Q base class. Reviewed-by:
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Oleksij Rempel authored
Protonic PRTI6Q is a development board and a base class for different specific customer application boards based on the i.MX6 family of SoCs, developed by Protonic Holland. Reviewed-by:
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Shengjiu Wang authored
Add ASRC device node. Signed-off-by:
Shengjiu Wang <shengjiu.wang@nxp.com> Signed-off-by:
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Krzysztof Kozlowski authored
Fix dtschema validator warnings like: l2-cache@a02000: $nodename:0: 'l2-cache@a02000' does not match '^(cache-controller|cpu)(@[0-9a-f,]+)*$' Signed-off-by:Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by:
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Krzysztof Kozlowski authored
Fix dtschema validator warnings like: l2-cache@40006000: $nodename:0: 'l2-cache@40006000' does not match '^(cache-controller|cpu)(@[0-9a-f,]+)*$' Signed-off-by:Stefan Agner <stefan@agner.ch> Signed-off-by:
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Shengjiu Wang authored
Add MQS support. As the pin conflict with usdhc2, then need to add a separate dts. Signed-off-by:
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Biwen Li authored
The patch add ftm_alarm0 DT node - add rcpm node - add ftm_alarm0 node - aliases ftm_alarm0 as rtc1 Signed-off-by:
Biwen Li <biwen.li@nxp.com> Signed-off-by:
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Shengjiu Wang authored
Complete the ESAI node and Add cs42888 sound card support. Signed-off-by:
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Shengjiu Wang authored
Add SPDIF support. Signed-off-by:
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Shengjiu Wang authored
Add SPDIF support. Signed-off-by:
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Shengjiu Wang authored
Add compatible string, update the clock table, add fsl,asrc-rate and fsl,asrc-width property. Signed-off-by:
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Ian Ray authored
Use kernel LED interface for the alarm LEDs. Signed-off-by:
Ian Ray <ian.ray@ge.com> Signed-off-by:
Samu Nuutamo <samu.nuutamo@vincit.fi> Signed-off-by:
Sebastian Reichel <sebastian.reichel@collabora.com> Signed-off-by:
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Shengjiu Wang authored
In imx6sll.dtsi, the ssi node name is different with other platforms (imx6qdl, imx6sl, imx6sx), but the sound/soc/fsl/fsl-asoc-card.c machine driver needs to check ssi node name for audmux configuration, then different ssi node name causes issue on imx6sll platform. So we change ssi node name to make all platforms have same name. Signed-off-by:
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Anson Huang authored
Change i.MX6/i.MX7 SoCs usdhc node name from usdhc to mmc to be compliant with yaml schema, it requires the nodename to be "mmc". Signed-off-by:
Anson Huang <Anson.Huang@nxp.com> Signed-off-by:
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Anson Huang authored
Change i.MX2/i.MX3/i.MX5 SoCs esdhc node name from esdhc to mmc to be compliant with yaml schema, it requires the nodename to be "mmc". Signed-off-by:
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Anson Huang authored
Change i.MX27/i.MX31 node name from sdhci to mmc to be compliant with yaml schema, it requires the nodename to be "mmc". Signed-off-by:
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Anson Huang authored
In latest i.MX6Q RM Rev.6, 05/2020, #90 SPI interrupt is reserved, so remove it from GPC node. Signed-off-by:
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Anson Huang authored
Change IIM node name from iim to efuse to be compliant with yaml schema, it requires the nodename to be one of "eeprom|efuse|nvram". Signed-off-by:
Fugang Duan <fugang.duan@nxp.com> Signed-off-by:
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Anson Huang authored
Change OCOTP node name from ocotp to efuse to be compliant with yaml schema, it requires the nodename to be one of "eeprom|efuse|nvram". Signed-off-by:
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Anson Huang authored
Change OCOTP node name from ocotp-ctrl to efuse to be compliant with yaml schema, it requires the nodename to be one of "eeprom|efuse|nvram". Signed-off-by:
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Yangbo Lu authored
The timer fixed interval period pulse generator register is used to generate periodic pulses. The down count register loads the value programmed in the fixed period interval (FIPER). At every tick of the timer accumulator overflow, the counter decrements by the value of TMR_CTRL[TCLK_PERIOD]. It generates a pulse when the down counter value reaches zero. It reloads the down counter in the cycle following a pulse. To use the TMR_FIPER register to generate desired periodic pulses. The value should programmed is, desired_period - tclk_period Current tmr-fiper2 value is to generate 100us periodic pulses. (But the value should have been 99995, not 99990. The tclk_period is 5.) This patch is to generate 1 second periodic pulses with value 999999995 programmed which is more desired by user. Signed-off-by:
Yangbo Lu <yangbo.lu@nxp.com> Acked-by:
Richard Cochran <richardcochran@gmail.com> Signed-off-by:
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Anson Huang authored
i.MX6/7 SoCs' temperature sensor is inside anatop module from HW perspective, so it should be a child node of anatop. Signed-off-by:
Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by:
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- Jun 23, 2020
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Andrey Smirnov authored
According to Vybrid Security RM, CCM_CCGR11[CG176] can be used to gate CAAM ipg clock. Signed-off-by:
Horia Geantă <horia.geanta@nxp.com> Signed-off-by:
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Peng Fan authored
Add mu root clk for mu mailbox usage. Reviewed-by:
Peng Fan <peng.fan@nxp.com> Acked-by:
Stephen Boyd <sboyd@kernel.org> Signed-off-by:
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