1. Jun 03, 2014
    • Fugang Duan's avatar
      i2c: imx: update i2c clock divider for each transaction · 9b2a6da3
      Fugang Duan authored
      
      
      Since IMX serial SOCs support low bus freq mode, some clocks freq
      may change to save power. I2C needs to check the clock source and
      update the divider.
      
      For example:
      i.MX6SL I2C clk is from IPG_PERCLK which is sourced from IPG_CLK.
      Under normal operation, IPG_CLK is 66MHz, ipg_perclk is at 22MHz.
      In low bus freq mode, IPG_CLK is at 12MHz and IPG_PERCLK is down
      to 4MHz. So the I2C driver must update the divider register for
      each transaction when the current IPG_PERCLK is not equal to the
      clock of previous transaction.
      
      Signed-off-by: default avatarFugang Duan <B38611@freescale.com>
      [wsa: removed an outdated comment and simplified debug output]
      Signed-off-by: default avatarWolfram Sang <wsa@the-dreams.de>
      9b2a6da3
    • Fugang Duan's avatar
      i2c: imx: fix the i2c bus hang issue when do repeat restart · 054b62d9
      Fugang Duan authored
      Test i2c device Maxim max44009, datasheet is located at:
      http://www.maximintegrated.com/datasheet/index.mvp/id/7175
      
      
      
      The max44009 support repeat operation like:
      read -> repeat restart -> read/write
      
      The current i2c imx host controller driver don't support this
      operation that causes i2c bus hang due to "MTX" is cleared in
      .i2c_imx_read(). If "read" is the last message there have no problem,
      so the current driver supports all SMbus operation like:
      write -> repeat restart -> read/write
      
      IMX i2c controller for master receiver has some limitation:
      - If it is the last byte for one operation, it must generate STOP
        signal before read I2DR to prevent controller from generating another
        clock cycle.
      - If it is the last byte in the read, and then do repeat restart, it must
        set "MTX" before read I2DR to prevent controller from generating another
        extra clock cycle.
      
      The patch is to fix the issue.
      
      Signed-off-by: default avatarFugang Duan <B38611@freescale.com>
      Signed-off-by: default avatarWolfram Sang <wsa@the-dreams.de>
      054b62d9
  2. Jun 02, 2014
  3. May 22, 2014