- May 25, 2023
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Vinod Koul authored
sc8180x pcie phy requires to describe six reg areas for the phy to work, so move the description to the correct place documenting tx, rx lane 1, 2 and pcs and pcs misc. Acked-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by:
Vinod Koul <vkoul@kernel.org> Link: https://lore.kernel.org/r/20230325122444.249507-4-vkoul@kernel.org Signed-off-by:
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- May 20, 2023
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Chunfeng Yun authored
These debugfs files are mainly used to make eye diagram test easier, especially helpful to do HQA test for a new IC without efuse enabled. Signed-off-by:
Chunfeng Yun <chunfeng.yun@mediatek.com> Link: https://lore.kernel.org/r/20230513092218.21139-2-chunfeng.yun@mediatek.com Signed-off-by:
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Chunfeng Yun authored
Add a debugfs root for phy class, and create a debugfs directory under the root when create phy, then phy drivers can add debugfs files. Signed-off-by:
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Li Jun authored
Add USB PHY parameter tuning for USB certifications. Reviewed-by:
Haibo Chen <haibo.chen@nxp.com> Signed-off-by:
Li Jun <jun.li@nxp.com> [j.zink: ported to v6.3-rc1 from NXP downstream repo + cleanups] Signed-off-by:
Johannes Zink <j.zink@pengutronix.de> Link: https://lore.kernel.org/r/20230516-lustige-usb-phy-dinge-v2-2-3383a0de34ac@pengutronix.de Signed-off-by:
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Johannes Zink authored
Add optional properties for tuning of usb phy. Signed-off-by:
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Bjorn Andersson authored
The QMP combo PHY sits in an of_graph connected between the DisplayPort controller and a USB Type-C connector (or possibly a redriver). The TCPM needs to be able to convey the HPD signal to the DisplayPort controller, but no directly link is provided by DeviceTree so the signal needs to "pass through" the QMP combo phy. Handle this by introducing a drm_bridge which upon initialization finds the next bridge (i.e. the usb-c-connector) and chain this together. This way HPD changes in the connector will propagate to the DisplayPort driver. The connector bridge is resolved lazily, as the TCPM is expected to be able to resolve the typec mux and switch at probe time, so the QMP combo phy will probe before the TCPM. Acked-by:
Neil Armstrong <neil.armstrong@linaro.org> Tested-by:
Bryan O'Donoghue <bryan.odonoghue@linaro.org> Reviewed-by:
Abel Vesa <abel.vesa@linaro.org> Tested-by:
Steev Klimaszewski <steev@kali.org> Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on HDK8450 Tested-by: Johan Hovold <johan+linaro@kernel.org> # X13s Reviewed-by:
Johan Hovold <johan+linaro@kernel.org> Signed-off-by:
Bjorn Andersson <quic_bjorande@quicinc.com> Link: https://lore.kernel.org/r/20230515032743.400170-7-quic_bjorande@quicinc.com Signed-off-by:
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Bjorn Andersson authored
The data lanes of the QMP PHY is swapped in order to handle changing orientation of the USB Type-C cable. Register a typec_switch device to allow a TCPM to configure the orientation. The newly introduced orientation variable is adjusted based on the request, and the initialized components are brought down and up again. To keep track of what parts needs to be cycled new variables to keep track of the individual init_count is introduced. Both the USB and the DisplayPort altmode signals are properly switched. For DisplayPort the controller will after the TCPM having established orientation power on the PHY, so this is not done implicitly, but for USB the PHY typically is kept initialized across the switch, and must therefore then be reinitialized. This is based on initial work by Wesley Cheng. Link: https://lore.kernel.org/r/20201009082843.28503-3-wcheng@codeaurora.org/ Reviewed-by:
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Bjorn Andersson authored
In multiple places throughout the driver code has been written in prepration for handling of orientation switching. Introduce a typec_orientation in qmp_combo and fill out the various "placeholders" with the associated logic. By initializing the orientation to "normal" this change has no functional impact, but reduces the size of the upcoming introduction of dynamic orientation switching. Reviewed-by:
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Bjorn Andersson authored
The phy core ensures mutual exclusion across the ops for a given phy, but the upcoming introduction of USB Type-C orientation switching might race with the DisplayPort phy operations. So extend the mutual exclusion to cover the remaining ops as well, to avoid concurrent reconfiguration of the hardware. Reported-by:
Johan Hovold <johan@kernel.org> Reviewed-by:
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Bjorn Andersson authored
With the upcoming introduction of USB Type-C orientation switching the region of mutual exclusion needs to be extended to cover both the common init/exit as well as the individual functions. So move the phy_mutex one step up the stack. Reviewed-by:
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Bjorn Andersson authored
The QMP combo phy can be connected to a TCPM, a USB controller and a DisplayPort controller for handling USB Type-C orientation switching and propagating HPD signals. Extend the binding to allow these connections to be described. Tested-by:
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Vinod Koul authored
This brings in the Qcom qmp patch fixes into next as well
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Frank Li authored
Add cdns,usb2-disconnect-threshold-microvolt property to address fake USB disconnection issue during enumeration or suspend state for difference platform. Reviewed-by:
Frank Li <Frank.Li@nxp.com> Link: https://lore.kernel.org/r/20230517161646.3418250-7-Frank.Li@nxp.com Signed-off-by:
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Frank Li authored
Add cdns,usb2-disconnect-threshold-microvolt property to address fake USB disconnection issue during enumeration or suspend state for difference platform. Signed-off-by:
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Peter Chen authored
For NXP platform design, the PHY can't know VBUS well, it causes the FSM in controller seeing the disconnection at L1 use case. With .set_mode API introduced, the controller driver could force PHY seeing B Session VALID when it is at the device mode (VBUS is there), and keep FSM working well. Signed-off-by:
Peter Chen <peter.chen@nxp.com> Signed-off-by:
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Peter Chen authored
Very limited parts may fail to work on full speed mode (both host and device modes) for USB3 port due to higher threshold in full speed receiver of USB2.0 PHY. One example failure symptom is, the enumeration is failed when connecting full speed USB mouse to USB3 port, especially under high temperature. The workaround is to configure threshold voltage value of single ended receiver by setting USB2.0 PHY register AFE_RX_REG5[2:0] to 3'b101. Signed-off-by:
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Peter Chen authored
For USB2 L1 use cases, some hosts may start transferring less than 20us after End of Resume, it causes the host seeing corrupt packet from the device side. The reason is the delay time between PHY powers up and txvalid is 20us. To fix it, we change the delay value as 0us. Signed-off-by:
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Peter Chen authored
There is an offset for USB2PHY in SALVO phy, add offset parameter for read and write API to cover both USB2 and USB3 PHY control. Signed-off-by:
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- May 17, 2023
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Bhupesh Sharma authored
Add support for the new qcm2290 / sm6115 binding. The USB QMP phy on these devices supports 2 lanes. Note that the binding now does not describe every register subregion and instead the driver holds the corresponding offsets. While at it also include support for PCS_MISC region which was left out earlier. Signed-off-by:
Bhupesh Sharma <bhupesh.sharma@linaro.org> Link: https://lore.kernel.org/r/20230516150511.2346357-3-bhupesh.sharma@linaro.org Signed-off-by:
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Bhupesh Sharma authored
'qcom,msm8996-qmp-usb3-phy.yaml' defines bindings for several PHYs which predate USB -> USB+DP migration. Since SM6115 and QCM2290 nodes for USB QMP phy are being added to dtsi files by followup patches, move these bindings instead to the newer style 'qcom,sc8280xp-qmp-usb3-uni-phy.yaml' file. Since no device trees use these bindings presently, so we have no ABI breakages with this patch. Signed-off-by:
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- May 16, 2023
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Siddharth Vadapalli authored
TI's J784S4 SoC supports USXGMII mode with the CPSW9G instance's MAC ports 1 and 2. Add USXGMII mode to the extra_modes member of J784S4's SoC data. Signed-off-by:
Siddharth Vadapalli <s-vadapalli@ti.com> Reviewed-by:
Roger Quadros <rogerq@kernel.org> Link: https://lore.kernel.org/r/20230331062521.529005-3-s-vadapalli@ti.com Signed-off-by:
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Siddharth Vadapalli authored
Each of the CPSW9G ports in TI's J784S4 SoC support modes such as QSGMII. Add a new compatible for it and allow the usage of "ti,qsgmii-main-ports" property for J784S4. Signed-off-by:
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Siddharth Vadapalli authored
TI's J721E SoC supports SGMII mode with the CPSW9G instance of the CPSW Ethernet Switch. Thus, enable it by adding SGMII mode to the list of the corresponding extra_modes member. Signed-off-by:
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Siddharth Vadapalli authored
TI's J7200 SoC supports SGMII mode with the CPSW5G instance of the CPSW Ethernet Switch. Thus, enable it by adding SGMII mode to the list of the corresponding extra_modes member. Signed-off-by:
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Siddharth Vadapalli authored
Add support to configure the CPSW MAC's PHY in SGMII mode if the SoC supports it. The extra_modes member of the phy_gmii_sel_soc_data struct corresponding to the SoC is used to determine whether or not the SoC supports SGMII mode. Signed-off-by:
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Yang Li authored
Convert platform_get_resource(),devm_ioremap_resource() to a single call to devm_platform_ioremap_resource(), as this is exactly what this function does. Signed-off-by:
Yang Li <yang.lee@linux.alibaba.com> Link: https://lore.kernel.org/r/20230428052758.38636-1-yang.lee@linux.alibaba.com Signed-off-by:
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Krzysztof Kozlowski authored
Update kerneldoc of struct qcom_snps_hsphy to fix: drivers/phy/qualcomm/phy-qcom-snps-femto-v2.c:135: warning: Function parameter or member 'update_seq_cfg' not described in 'qcom_snps_hsphy' Signed-off-by:
Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20230507144818.193039-1-krzysztof.kozlowski@linaro.org Signed-off-by:
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Neil Armstrong authored
Use the same CNTL2_DIF_TX_CTL0 value used by the vendor, it was reported fixing timings issues. Fixes: 2a56dc65 ("phy: amlogic: Add G12A Analog MIPI D-PHY driver") Signed-off-by:
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Tom Rix authored
gcc on aarch64 reports drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c: In function ‘mtk_hdmi_pll_set_rate’: drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c:240:52: error: ‘-mgeneral-regs-only’ is incompatible with the use of floating-point types 240 | else if (tmds_clk >= 54 * MEGA && tmds_clk < 148.35 * MEGA) Floating point should not be used, so rework the floating point comparisons to fixed point. Signed-off-by:
Tom Rix <trix@redhat.com> Reviewed-by:
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David Yang authored
Support for inno-usb2-phy on Hi3798MV100 was added into existing driver, while Hi3798MV100 is a A9 ARM32-only SoC. Signed-off-by:
David Yang <mmyangfl@gmail.com> Link: https://lore.kernel.org/r/20230509060449.1151113-3-mmyangfl@gmail.com Signed-off-by:
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David Yang authored
Adopt existing phy-hisi-inno-usb2 driver to Hi3798MV100, with a slightly different TEST register convention. Signed-off-by:
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Artur Weber authored
Support for the Exynos4212 SoC was originally dropped as there were no boards using it. We will be adding a device that uses it, so add it back. This reverts commit fee7e1d5 . Signed-off-by:
Artur Weber <aweber.kernel@gmail.com> Reviewed-by:
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Varadarajan Narayanan authored
Updated USB QMP PHY Init sequence based on HPG for IPQ9574. Reused clock and reset list from existing targets. Reviewed-by:
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by:
Praveenkumar I <quic_ipkumar@quicinc.com> Signed-off-by:
Varadarajan Narayanan <quic_varada@quicinc.com> Link: https://lore.kernel.org/r/4f15c21f28e2a1332fbdb04d60641cbbf05c6f15.1683630932.git.quic_varada@quicinc.com Signed-off-by:
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Varadarajan Narayanan authored
Add the phy init sequence for the Super Speed ports found on IPQ9574. Reviewed-by:
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Varadarajan Narayanan authored
* Add dt-bindings for USB3 PHY found on Qualcomm IPQ9574 * Making power-domains as optional since IPQ9574 doesn't have GDSCs Signed-off-by:
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Varadarajan Narayanan authored
Document the compatible string used for the qusb2 phy in IPQ9574. Acked-by:
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- May 08, 2023
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Daniel Machon authored
Add a check for skip_cmu_cfg when configuring the serdes lane. All individual serdeses are reset upon first configuration. Resetting the serdes involves reconfiguring it with preset values. The serdesmode is required to determine the clock-providing CMU, therefore make sure the serdes is not reconfigured if the serdesmode is not set. Signed-off-by:
Daniel Machon <daniel.machon@microchip.com> Link: https://lore.kernel.org/r/20230417180335.2787494-8-daniel.machon@microchip.com Signed-off-by:
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Daniel Machon authored
CMUs should not be powered up by default anymore, so remove responsible code. Signed-off-by:
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Daniel Machon authored
Power on the CMU instance, that provides the clock for the serdes, given the specified serdes mode and index. The CMU instance is looked up, using a preset map of serdes mode and index to CMU index. Signed-off-by:
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Daniel Machon authored
All CMUs are powered up initially. This uses needless power. This patch makes sure all CMUs are powered down by default. This involves configuring a number reference clock and power-down registers of the CMU. Individual CMUs are later powered up, when the serdes lanes are configured. Signed-off-by:
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