- Dec 03, 2014
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Matthieu Crapet authored
When a pin is configured as GPIO, print also direction (input or output). Signed-off-by:
Matthieu Crapet <mcrapet@gmail.com> Signed-off-by:
Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by:
Linus Walleij <linus.walleij@linaro.org>
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- Nov 27, 2014
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Beniamino Galvani authored
Add device tree bindings documentation for Amlogic Meson pin and GPIO controller. Signed-off-by:
Beniamino Galvani <b.galvani@gmail.com> Signed-off-by:
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Dmitry Torokhov authored
irq_of_parse_and_map() returns 0 on error, so testing for negative result never works. Signed-off-by:
Dmitry Torokhov <dtor@chromium.org> Acked-by:
James Hogan <james.hogan@imgtec.com> Signed-off-by:
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James Hogan authored
Fix a typo, s/which which/which/ in the img,tz1090-pinctrl.txt binding. Signed-off-by:
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- Nov 11, 2014
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Soren Brinkmann authored
Signed-off-by:
Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by:
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Linus Walleij authored
Merge tag 'for_3.19/samsung-pinctrl' of git://git.kernel.org/pub/scm/linux/kernel/git/tfiga/samsung-pinctrl into devel Samsung pinctrl patches for v3.19 1) pinctrl-samsung data structure clean-up 8100cf47 pinctrl: samsung: Separate per-bank init and runtime data 1bf00d7a pinctrl: samsung: Constify samsung_pin_ctrl struct 94ce944b pinctrl: samsung: Constify samsung_pin_bank_type struct e06deff9 pinctrl: samsung: Drop unused label field in samsung_pin_ctrl struct 87993273 pinctrl: samsung: Make samsung_pinctrl_get_soc_data use ERR_PTR() 2) pinctrl-samsung Exynos7 support 50cea0cf pinctrl: exynos: Add initial driver data for Exynos7 14c255d3 pinctrl: exynos: Add irq_chip instance for Exynos7 wakeup interrupts 6f5e41bd pinctrl: exynos: Consolidate irq domain callbacks 0d3d30db pinctrl: exynos: Generalize the eint16_31 demux code 3) pinctrl-samsung Exynos4415 support 2891ba29 pinctrl: exynos: Add support for Exynos4415
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- Nov 09, 2014
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Tomasz Figa authored
The pin controllers of Exynos4415 are similar to Exynos4412, but certain differences cause the need to create separate driver data for it. This patch adds pin controller and bank descriptor arrays to the driver to support the new SoC. Cc: Tomasz Figa <tomasz.figa@gmail.com> Cc: Thomas Abraham <thomas.abraham@linaro.org> Cc: Linus Walleij <linus.walleij@linaro.org> Signed-off-by:
Tomasz Figa <tomasz.figa@gmail.com> [cw00.choi: Rebase it on mainline kernel] Signed-off-by:
Chanwoo Choi <cw00.choi@samsung.com> Acked-by:
Kyungmin Park <kyungmin.park@samsung.com> [tomasz.figa@gmail.com: Resolved merge with earlier clean-up series.] Signed-off-by:
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Naveen Krishna Ch authored
This patch adds initial driver data for Exynos7 pinctrl support. Signed-off-by:
Naveen Krishna Ch <naveenkrishna.ch@gmail.com> Signed-off-by:
Abhilash Kesavan <a.kesavan@samsung.com> Reviewed-by:
Thomas Abraham <thomas.ab@samsung.com> Tested-by:
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Abhilash Kesavan authored
Exynos7 uses different offsets for wakeup interrupt configuration registers. So a new irq_chip instance for Exynos7 wakeup interrupts is added. The irq_chip selection is now based on the wakeup interrupt controller compatible string. Signed-off-by:
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Abhilash Kesavan authored
Adding a irq_chip field to the samsung_pin_bank struct helps in consolidating the irq domain callbacks for external gpio and wakeup interrupt controllers. The exynos_wkup_irqd_ops and exynos_gpio_irqd_ops have now been merged into a single exynos_eint_irqd_ops. Signed-off-by:
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Abhilash Kesavan authored
The function exynos_irq_demux_eint16_31 uses pre-defined offsets for external interrupt pending status and mask registers. So this function is not extensible for Exynos7 SoC which has these registers at different offsets. Generalize the exynos_irq_demux_eint16_31 function by using the pending/mask register offset values from the exynos_irq_chip structure. This is done by adding a irq_chip field to the samsung_pin_bank struct. Signed-off-by:
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Tomasz Figa authored
Currently the driver mixes constant init data with runtime data, which is far from being elegant and can invite potential hard to track issues. This patch intends to solve this by introducing a new samsung_pin_bank_data structure to hold only constant data known at compile time, which can be copied to main samsung_pin_bank struct used at runtime. In addition, thanks to this change, all per-bank initdata can be marked with const and __initconst keywords and dropped after init completes. Signed-off-by: -
Tomasz Figa authored
In order to separate initialization constants from runtime data, this patch modifies the driver to store only constant data in samsung_pin_ctrl struct and copy data required at runtime to samsung_pinctrl_drv_data struct. This makes it possible to mark all existing instances of samsung_pin_ctrl struct as const and __initconst. Signed-off-by: -
Tomasz Figa authored
This structure is not intended to be modified at runtime and functions as constant data shared between multiple pin banks. This patch makes all instances of it constant across the driver. Signed-off-by: -
Tomasz Figa authored
There is no code using it and in fact there are pin controller variants that do not even have this field initialized in their init data. This patch removes it completely. Signed-off-by: -
Tomasz Figa authored
Currently the function returns a valid pointer on success and NULL on error, so exact error code is lost. This patch changes return convention of the function to use ERR_PTR() on error instead. Signed-off-by:
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- Nov 04, 2014
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Mika Westerberg authored
This driver supports the pin/GPIO controllers found in newer Intel SoCs like Cherryview and Braswell. The driver provides full GPIO support and minimal set of pin controlling funtionality. The driver is based on the original Cherryview GPIO driver authored by Ning Li and Alan Cox. Signed-off-by:
Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by:
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Mika Westerberg authored
The GPIO resources (GpioIo/GpioInt) used in ACPI contain a GPIO number which is relative to the hardware GPIO controller. Typically this number can be translated directly to Linux GPIO number because the mapping is pretty much 1:1. However, when the GPIO driver is using pins exported by a pin controller driver via set of GPIO ranges, the mapping might not be 1:1 anymore and direct translation does not work. In such cases we need to translate the ACPI GPIO number to be suitable for the GPIO controller driver in question by checking all the pin controller GPIO ranges under the given device and using those to get the proper GPIO number. Signed-off-by:
Rafael J. Wysocki <rafael.j.wysocki@intel.com> Signed-off-by:
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Yingjoe Chen authored
Fix pinconfig include file path. Signed-off-by:
Yingjoe Chen <yingjoe.chen@mediatek.com> Signed-off-by:
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- Nov 03, 2014
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Linus Walleij authored
Merge tag 'v3.19-rockchip-pinctrl1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into devel Rockchip-pinctrl fixes from Doug Anderson and suspend-specific functions from Chris Zhong
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- Nov 01, 2014
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Chris Zhong authored
Save and restore the gpio6_c6 pinmux setting, since Maskrom of RK3288 would modify it to sdmmc0_det, so it need to be restored to the correct setting after resume from Maskrom. Signed-off-by:
Chris Zhong <zyw@rock-chips.com> Tested-by:
Doug Anderson <dianders@chromium.org> Reviewed-by:
Heiko Stuebner <heiko@sntech.de> Signed-off-by:
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Chris Zhong authored
support suspend/resume of pinctrl, it allows handling sleep mode for hogged pins in pinctrl Signed-off-by:
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- Oct 31, 2014
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Varka Bhadram authored
Sanity check on resource happening with devm_ioremap_resource(). Signed-off-by:
Varka Bhadram <varkab@cdac.in> Signed-off-by:
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- Oct 30, 2014
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Maxime Ripard authored
The A80 has a rather usual pin controller, the only thing out of the ordinary being that it has 5 interrupts banks, and that some pins have several options for the same functions. Signed-off-by:
Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by:
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Maxime Ripard authored
The A80 R-PIO controller has one more bank that what we've seen so far, add the PN pin bank. Signed-off-by:
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Uwe Kleine-König authored
The mxs pinctrl driver cannot handle when functions are not grouped by name (which IMO is a bug). This happens for example if a imx28-somemachine.dts provides a function that has the same name as a function defined in imx28.dtsi. The proper way to fix that would be to check for duplicates in the loops (which increases parsing time) or parse the groups first and sort the resulting array. Signed-off-by:
Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Acked-by:
Shawn Guo <shawn.guo@linaro.org> Signed-off-by:
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Doug Anderson authored
There were a few instances where the rockchip pinctrl driver would do read-modify-write with no spinlock. Add a spinlock for these cases. Signed-off-by:
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Doug Anderson authored
Just like in (529301c1 pinctrl: samsung: Parse pin groups before calling pinctrl_register()), Rockchip also needs to parse pin groups earlier to make hogs work. Signed-off-by:
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Doug Anderson authored
The Rockchip pinctrl driver was calling rockchip_gpio_direction_output() in the pin_config_set() callback. This was just a shortcut for: * rockchip_gpio_set() * pinctrl_gpio_direction_output() Unfortunately it's not so good to call pinctrl_gpio_direction_output() from pin_config_set(). Specifically when initting hogs you'll get an error. Let's refactor a little so we can call _rockchip_pmx_gpio_set_direction() directly. Signed-off-by:
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Doug Anderson authored
The rockchip pinctrl driver uses irq_gc_set_wake() but doesn't setup the .wake_enabled member. That means that we can never actually use a pin for wakeup. When "irq_set_irq_wake()" tries to call through it will always get a failure from set_irq_wake_real() and will then set wake_depth to 0. Assuming you can resume you'll later get an error message about "Unbalanced IRQ x wake disable". Signed-off-by:
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- Oct 29, 2014
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Mika Westerberg authored
Add MAINTAINERS entry for Intel pin controller drivers. I will be maintaining them with Heikki, who kindly promised to help me with this. Signed-off-by:
Heikki Krogerus <heikki.krogerus@linux.intel.com> Signed-off-by:
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Mika Westerberg authored
We are going to have more pinctrl drivers for Intel hardware so separate all our pin controller drivers to own directory. Signed-off-by:
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Ivan T. Ivanov authored
This is the pinctrl, pinmux, pinconf and gpiolib driver for the Qualcomm MPP sub-function blocks found in the PMIC chips. Signed-off-by:
Ivan T. Ivanov <iivanov@mm-sol.com> Acked-by:
Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by:
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Ivan T. Ivanov authored
This is the pinctrl, pinmux, pinconf and gpiolib driver for the Qualcomm GPIO sub-function blocks found in the PMIC chips. Signed-off-by:
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Ivan T. Ivanov authored
DeviceTree binding documentation for Qualcomm SPMI PMIC MPP pinctrl drivers. Signed-off-by:
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Bjorn Andersson authored
This introduced the device tree bindings for the GPIO block found in PMIC's from Qualcomm. Signed-off-by:
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Alexandre Belloni authored
Copy the mach/at91_pio.h header locally and use it for pinctrl-at91.c. This allows to remove the dependency on mach/at91_pio.h to be able to move at91 to multiplatform. Signed-off-by:
Alexandre Belloni <alexandre.belloni@free-electrons.com> Acked-by:
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Varka Bhadram authored
Sanity check on resource happening with devm_ioremap_resource(). Signed-off-by:
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- Oct 28, 2014
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Soren Brinkmann authored
When dumping pinconf information in debugfs, config arguments are only printed when a unit is present and the argument is != 0. For parameters like the slew rate, this does not work. The slew rate uses a driver specific format for the argument, i.e. 0 can be a valid argument and a unit is not provided for it. For that reason, add a flag to enable printing the argument instead of inferring it from the presence of a unit and the value of the argument. Signed-off-by:
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Thierry Reding authored
The pinctrl config helpers make a separate copy of the configuration, so callers must make sure to free any dynamically allocated memory that was used to store it. Signed-off-by:
Thierry Reding <treding@nvidia.com> Signed-off-by:
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