- Jan 17, 2020
-
-
Olof Johansson authored
Merge tag 'tegra-for-5.6-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/dt arm64: tegra: Device tree changes for v5.6-rc1 These patches do some cleanup to existing nodes, add the memory subsystem on Tegra186 and Tegra194 as well as the FUSE and APB MISC nodes on Tegra194. There are also a few additions to the Jetson Nano device tree to enable additional features and the force recovery button on the Jetson AGX Xavier now produces a key code that is actually valid. Finally, an alias is added for the Ethernet card on Jetson TX2 to allow firmware to find it and pass a MAC address via device tree. * tag 'tegra-for-5.6-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: arm64: tegra: Allow bootloader to configure Ethernet MAC on Jetson TX2 arm64: tegra: Redefine force recovery key on Jetson AGX Xavier arm64: tegra: Enable SDIO on Jetson Nano M.2 Key E arm64: tegra: Enable PWM fan on Jetson Nano arm64: tegra: Add fuse/apbmisc node on Tegra194 arm64: tegra: Make XUSB node consistent with the rest arm64: tegra: Add the memory subsystem on Tegra194 arm64: tegra: Add external memory controller on Tegra186 arm64: tegra: Add interrupt for memory controller on Tegra186 arm64: tegra: Rename EMC on Tegra132 arm64: tegra: Let the EMC hardware use the EMC clock Link: https://lore.kernel.org/r/20200111003553.2411874-7-thierry.reding@gmail.com Signed-off-by:
Olof Johansson <olof@lixom.net>
-
Olof Johansson authored
Merge tag 'tegra-for-5.6-arm-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/dt ARM: tegra: Device tree changes for v5.6-rc1 This adds memory timings for the PAZ100 and does some minor cleanup for the external memory controller device tree node on Tegra124. * tag 'tegra-for-5.6-arm-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: ARM: dts: tegra20: paz00: Add memory timings ARM: tegra: Rename EMC on Tegra124 ARM: tegra: Let the EMC hardware use the EMC clock Link: https://lore.kernel.org/r/20200111003553.2411874-6-thierry.reding@gmail.com Signed-off-by:
-
Olof Johansson authored
Merge tag 'tegra-for-5.6-dt-bindings' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/dt dt-bindings: Changes for v5.6-rc1 This contains a conversion of the Tegra124 EMC bindings to json-schema as well as the addition of the bindings for the memory subsystem found on Tegra186 and Tegra194. * tag 'tegra-for-5.6-dt-bindings' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: dt-bindings: memory: Add Tegra186 memory subsystem dt-bindings: memory: Add Tegra194 memory controller header dt-bindings: memory: Add Tegra186 memory client IDs dt-bindings: memory-controller: Convert Tegra124 EMC to json-schema Link: https://lore.kernel.org/r/20200111003553.2411874-1-thierry.reding@gmail.com Signed-off-by:
-
- Jan 12, 2020
-
-
Olof Johansson authored
Merge tag 'samsung-dt-5.6' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into arm/dt Samsung DTS ARM changes for v5.6 1. Couple ARM and wcore bus regulators on Exynos542x so higher frequencies could be used with dynamic voltage and frequency scaling. Enable this higher frequencies. 2. Correct the polarity of USB3503 hub GPIOs. 3. Adjust the bus frequencies (scaled with devfreq framework) on Exynos5422 Odroid boards to match values possible to obtain from root PLLs. 4. Add display to Tiny4412 board. 5. Cleanups and minor improvements. * tag 'samsung-dt-5.6' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux: ARM: dts: exynos: Enable FIMD node and add proper panel node to Tiny4412 ARM: dts: samsung: Rename Samsung and Exynos to lowercase ARM: dts: exynos: Adjust bus related OPPs to the values correct for Exynos5422 Odroids ARM: dts: exynos: Move Exynos5420 bus related OPPs to the Odroid boards DTS ARM: dts: exynos: Correct USB3503 GPIOs polarity ARM: dts: exynos: Add missing CPU frequencies for Exynos5422/5800 ARM: dts: exynos: Add initial data for coupled regulators for Exynos5422/5800 ARM: dts: exynos: Remove syscon compatible from chipid node on Exynos5 Link: https://lore.kernel.org/r/20200110172334.4767-3-krzk@kernel.org Signed-off-by:
-
- Jan 11, 2020
-
-
Chunyan Zhang authored
We've created a vendor directory for sprd, so move the board bindings to there. Link: https://lore.kernel.org/r/20200110063755.19804-2-zhang.lyra@gmail.com Signed-off-by:
Chunyan Zhang <chunyan.zhang@unisoc.com> Acked-by:
Rob Herring <robh@kernel.org> Signed-off-by:
-
Olof Johansson authored
Merge tag 'v5.6-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into arm/dt New boards are the Radxa Rock Pi N10 using the VMARC SOM and Dalang carrier board, separate versions for the two rockpro64 hardware revisions which switched a pin between revisions. The rockpro64 also got bluetooth support now. The px30 got a lot of attention with dsi, gpu and thermal support. Similarly the rk3399-roc-pc board also got attention with mtd flash, sdr104 mode, hdmi sound, gpu and a lot of other smaller improvements. Other than that there is a new gpu-cooling device for rk3399 a cpu idle-state for rk3328 and more small improvements across a number of boards. * tag 'v5.6-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: (37 commits) arm64: dts: rockchip: Enable mp8859 regulator on rk3399-roc-pc arm64: dts: rockchip: rk3399-hugsun-x99: remove supports-sd and supports-emmc options arm64: dts: rockchip: rk3399-firefly: remove num-slots from &sdio0 node arm64: dts: rockchip: Add PX30 LVDS arm64: dts: rockchip: add dsi controller for px30 arm64: dts: rockchip: Add PX30 DSI DPHY arm64: dts: rockchip: Add RK3328 idle state arm64: dts: rockchip: remove identical &uart0 node from rk3368-lion-haikou arm64: dts: rockchip: Add Radxa Rock Pi N10 initial support ARM: dts: rockchip: Add Radxa Dalang Carrier board arm64: dts: rockchip: Add VMARC RK3399Pro SOM initial support dt-bindings: arm: rockchip: Add Rock Pi N10 binding arm64: dts: rockchip: hook up bluetooth at uart0 on rockpro64 arm64: dts: rockchip: enable wifi module at sdio0 on rockpro64 arm64: dts: rockchip: split rk3399-rockpro64 for v2 and v2.1 boards arm64: dts: rockchip: enable the gpu on px30-evb arm64: dts: rockchip: add the gpu for px30 dt-bindings: gpu: mali-bifrost: Add Rockchip PX30 arm64: dts: rockchip: Add GPU cooling device for RK3399 arm64: dts: rockchip: Add regulators for PCIe for Radxa Rock Pi 4 board ... Link: https://lore.kernel.org/r/5115625.yBEeHQkg2z@phil Signed-off-by:
-
Olof Johansson authored
Merge tag 'v5.6-rockchip-dts32-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into arm/dt Pin-name corrections for Veyron-Fievel, bluetooth for a number of veyron boards and additional operating points for rk3288-tinker. * tag 'v5.6-rockchip-dts32-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: ARM: dts: rockchip: Use ABI name for recovery mode pin on veyron fievel/tiger ARM: dts: rockchip: Use ABI name for write protect pin on veyron fievel/tiger ARM: dts: rockchip: Add missing cpu operating points for rk3288-tinker ARM: dts: rockchip: Add brcm bluetooth for rk3288-veyron Link: https://lore.kernel.org/r/8215452.dU6eVM2tAM@phil Signed-off-by:
-
Amelie Delaunay authored
This enables the driver for STM32 PWR regulators found on stm32mp1. Link: https://lore.kernel.org/r/20200109125531.13610-1-alexandre.torgue@st.com Signed-off-by:
Amelie Delaunay <amelie.delaunay@st.com> Signed-off-by:
Alexandre Torgue <alexandre.torgue@st.com> Signed-off-by:
-
Olof Johansson authored
Merge tag 'stm32-dt-for-v5.6-1' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32 into arm/dt STM32 DT updates for v5.6, round 1 Highlights: ---------- MPU part: -Add PWM support on DK2 board. -Add counter support to STM32 timers. -Add support of SDMMC 2&3 instances based on "arm,pl18x". SDMMC2 is connected to eMMC on ED1 board. SDMMC3 is connected to the GPIO extension connector on EV1 & DKx boards. -Add ADC support on ED1 board. -Update devicetree files split to better fit to STM32MP15 SOC & boards diversity. -Fix issues seen during YAML validation. -Enable Ethernet (MAC) TX clock gating during low-power mode. -Enable USB OTG HS support on DKx boards. -Enable USB Host EHCI on DKx boards. MCU part: -Fix issues seen during YAML validation. * tag 'stm32-dt-for-v5.6-1' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32: (37 commits) ARM: dts: stm32: Add power-supply for RGB panel on stm32429i-eval ARM: dts: stm32: Add power-supply for DSI panel on stm32f469-disco ARM: dts: stm32: change nvmem node name on stm32mp1 ARM: dts: stm32: change nvmem node name on stm32f429 ARM: dts: stm32: update mlahb node according to the bindings on stm32mp15 ARM: dts: stm32: fix dma controller node name on stm32mp157c ARM: dts: stm32: fix dma controller node name on stm32f743 ARM: dts: stm32: fix dma controller node name on stm32f746 ARM: dts: stm32: add phy-names to usbotg_hs on stm32mp157c-ev1 ARM: dts: stm32: enable USB OTG HS on stm32mp15 DKx boards ARM: dts: stm32: enable USB Host (USBH) EHCI controller on stm32mp15 DKx ARM: dts: stm32: enable USBPHYC on stm32mp15 DKx boards ARM: dts: stm32: remove useless clock-names from RTC node on stm32f746 ARM: dts: stm32: remove useless clock-names from RTC node on stm32f429 ARM: dts: stm32: Enable MAC TX clock gating during TX low-power mode on stm32mp15 ARM: dts: stm32: adjust slew rate for Ethernet on stm32mp15 ARM: dts: stm32: remove syscfg clock on stm32mp15 ethernet ARM: dts: stm32: remove "@" and "_" from stm32f7 pinmux groups ARM: dts: stm32: remove "@" and "_" from stm32f4 pinmux groups ARM: dts: stm32: Adapt STM32MP157C ED1 board to STM32 DT diversity ... Link: https://lore.kernel.org/r/39df1dee-3c9f-cd35-bc55-a71223e07100@st.com Signed-off-by:
-
git://github.com/hisilicon/linux-hisiOlof Johansson authored
ARM64: DT: Hisilicon SoCs DT updates for 5.6 - Add remote control map name of the IR device for the hi3798cv200 poplar board - Correct the PCIe bus range setting for the hi3798cv200 * tag 'hisi-arm64-dt-for-5.6' of git://github.com/hisilicon/linux-hisi: arm64: dts: hi3798cv200: correct PCIe 'bus-range' setting arm64: dts: hi3798cv200-poplar: add linux,rc-map-name for IR Link: https://lore.kernel.org/r/5E169EDE.8020809@hisilicon.com Signed-off-by:
-
https://github.com/Broadcom/stblinuxOlof Johansson authored
This pull request contains Broadcom ARM-based SoCs Device Tree changes for 5.6, please pull the following: - Stephan adds support for the HWRNG on 2711 (Raspberry Pi 4) which is different than the previous Pi chips - Florian switches the BCM956265HR board to use the hardware I2C controllers for interfacing with the SFPs * tag 'arm-soc/for-5.6/devicetree' of https://github.com/Broadcom/stblinux: ARM: dts: bcm2711: Enable HWRNG support ARM: dts: bcm2835: Move rng definition to common location ARM: dts: NSP: Use hardware I2C for BCM958625HR Link: https://lore.kernel.org/r/20200108191114.15987-1-f.fainelli@gmail.com Signed-off-by:
-
Peter Robinson authored
Add an ethernet alias so that a stable MAC address is added to the device tree for the wired ethernet interface. Signed-off-by:
Peter Robinson <pbrobinson@gmail.com> Signed-off-by:
Thierry Reding <treding@nvidia.com>
-
- Jan 10, 2020
-
-
Thierry Reding authored
The current BTN_1 code associated with the force-recovery key is not a valid code for EV_KEY type input devices. This causes errors in the libinput debug-events command. There is no system level action that maps to the force-recovery key on Jetson AGX Xavier, so assign it the KEY_SLEEP action, which at least makes it do something marginally useful. Signed-off-by: -
Tamás Szűcs authored
Enable SDMMC3 and set it up for SDIO devices. Signed-off-by:
Tamás Szűcs <tszucs@protonmail.ch> Signed-off-by:
-
Tamás Szűcs authored
Enable PWM fan and extend CPU thermal zones for monitoring and fan control. This will trigger the PWM fan on J15 and cool down the system if necessary. Signed-off-by:
-
Dmitry Osipenko authored
PAZ00 board has two variants of DDR2 SDRAM devices for External Memory: one is Hynix HY5PS1G831CLFP-Y5 and the other is Micron MT47H128M8CF-25:H. The Micron variant doesn't have official timings in the wild, hence only timings for the Hynix are added. The memory frequency-scaling was tested using the Tegra20 devfreq driver. Tested-by:
Marc Dietrich <marvin24@gmx.de> Signed-off-by:
Dmitry Osipenko <digetx@gmail.com> Signed-off-by:
-
JC Kuo authored
This commit adds Tegra194 fuse and apbmisc device nodes. Signed-off-by:
JC Kuo <jckuo@nvidia.com> Signed-off-by:
-
Thierry Reding authored
The ordering of properties in the XUSB node is inconsistent with the ordering of the properties in other nodes. Resort them to make the node more consistent. Also get rid of some unnecessary whitespace. Signed-off-by: -
Thierry Reding authored
The memory subsystem on Tegra194 encompasses both the memory and external memory controllers. The EMC is represented as a subnode of the MC and a ranges property is used to describe the register ranges. A dma-ranges property is also added to describe that all memory clients can address up to 39 bits using the memory controller client interface (MCCIF), unless otherwise limited by the DMA engines of the hardware. A memory client can technically use 40 bits of addresses, but the memory controller on Tegra194 uses bit 39 to determine the XBAR format used to access memory. Use of this bit needs to be explicitly controlled by the operating system drivers for devices that can use this on-the-fly format conversion. Using the dma-ranges property prevents the operating system from using the bit implicitly, for example in I/O virtual address mappings. Signed-off-by: -
Thierry Reding authored
Add the external memory controller as a child device of the memory controller on Tegra186. The memory controller really represents the memory subsystem that encompasses both the memory and external memory controllers. The external memory controller uses the BPMP to obtain the list of supported EMC frequencies and set the EMC frequency. Also set up the dma-ranges property to describe that all memory clients can address up to 40 bits using the memory controller client interface (MCCIF), unless otherwise limited by the DMA engines of the hardware. Signed-off-by: -
Thierry Reding authored
The memory controller can be interrupted by certain conditions. Add the interrupt to the device tree node to allow drivers to trap these conditions. Signed-off-by: -
Thierry Reding authored
The NVIDIA Tegra186 SoC contains a memory subsystem composed of the memory controller and the external memory controller. The memory controller provides interfaces for the memory clients to access the memory. Accesses can be either bounced through the SMMU for IOVA translation or directly to the EMC. The bulk of the programming of the external memory controller happens through interfaces exposed by the BPMP. Describe this relationship by adding a phandle reference to the BPMP to the EMC node. Signed-off-by:
-
Thierry Reding authored
This header contains definitions for the memory controller found on NVIDIA Tegra194 SoCs, such as the stream IDs used for the ARM SMMU and the IDs used to identify the various memory clients. Signed-off-by:
-
Thierry Reding authored
Add IDs for the memory clients found on NVIDIA Tegra186 SoCs. This will be used to describe interconnect paths from devices to system memory. Signed-off-by:
-
Thierry Reding authored
Rename the EMC node to external-memory-controller according to device tree best practices. Signed-off-by: -
Thierry Reding authored
Rename the EMC node to external-memory-controller according to device tree best practices. Signed-off-by: -
Thierry Reding authored
The EMC hardware block needs access to the EMC clock in order to scale the external memory frequency. Add the clocks property so that drivers for the EMC can acquire a reference to the EMC clock. Signed-off-by: -
Thierry Reding authored
The EMC hardware block needs access to the EMC clock in order to scale the external memory frequency. Add the clocks property so that drivers for the EMC can acquire a reference to the EMC clock. Signed-off-by: -
Thierry Reding authored
Convert the device tree bindings for the Tegra124 EMC controller to the DT schema format using json-schema. While at it, clean up the binding a little bit by removing any mention of how RAM code and clock frequency are represented in unit-addresses (which they aren't) and by adding the EMC clock without which the EMC controller can't change the frequency at which the external memory is clocked. While this is technically an ABI break (the clock was not required before), this should be fine because there isn't much that the EMC driver can do without access to the EMC clock. Signed-off-by:
-
- Jan 09, 2020
-
-
Benjamin Gaignard authored
Add a fixed regulator and use it as power supply for RBG panel. Signed-off-by:
Benjamin Gaignard <benjamin.gaignard@st.com> Signed-off-by:
-
Benjamin Gaignard authored
Add a fixed regulator and use it as power supply for DSI panel. Fixes: 18c88662 ("ARM: dts: stm32: Add display support on stm32f469-disco") Signed-off-by:
-
Benjamin Gaignard authored
Change non volatile node name from nvmem to efuse to be compliant with yaml schema. Signed-off-by:
-
Benjamin Gaignard authored
Change non volatile node name from nvmem to efuse to be compliant with yaml schema. Signed-off-by:
-
Arnaud Pouliquen authored
Update of the mlahb node according to to DT bindings using json-schema Signed-off-by:
Arnaud Pouliquen <arnaud.pouliquen@st.com> Signed-off-by:
-
Benjamin Gaignard authored
Modify dma controller nodes name to fit with the standard naming. Signed-off-by:
-
Benjamin Gaignard authored
Modify dma controller nodes name to fit with the standard naming. Signed-off-by:
-
Benjamin Gaignard authored
Modify dma controller nodes name to fit with the standard naming. Signed-off-by:
-
Amelie Delaunay authored
phy-names is required by usbotg_hs driver to get the phy, otherwise, it considers that there is no phys property. Signed-off-by:
-
Amelie Delaunay authored
This patch enables USB OTG HS on stm32mp15 dkx in Peripheral mode. Signed-off-by:
-
Amelie Delaunay authored
This patch enables USB Host (USBH) EHCI controller on stm32mp15 dk boards. As a hub is used between USBH and USB connectors, no need to enable USBH OHCI controller: all low- and full-speed traffic is managed by the hub. Signed-off-by:
-
