- Dec 22, 2016
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Gabriel Fernandez authored
In the stm32f469 soc, the 48Mhz clock could be derived from pll-q or from pll-sai-p. The SDIO clock could be also derived from 48Mhz or from sys clock. Signed-off-by:
Gabriel Fernandez <gabriel.fernandez@st.com> Signed-off-by:
Stephen Boyd <sboyd@codeaurora.org>
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Gabriel Fernandez authored
This patch introduces SAI clocks for stm32f4 socs. Signed-off-by:
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Gabriel Fernandez authored
This patch introduces I2S clock for stm32f4 soc. The I2S clock could be derived from an external clock or from pll-i2s Signed-off-by:
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Gabriel Fernandez authored
This patch introduces lcd-tft clock for stm32f4 soc. Signed-off-by:
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Gabriel Fernandez authored
This patch adds post dividers of I2S & SAI PLLs. These dividers are managed by a dedicated register (RCC_DCKCFGR). The PLL should be off before a set rate. Signed-off-by:
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Gabriel Fernandez authored
This patch introduces PLL_I2S and PLL_SAI. Vco clock of these PLLs can be modify by DT (only n multiplicator, m divider is still fixed by the boot-loader). Each PLL has 3 dividers. PLL should be off when we modify the rate. Signed-off-by:
Rob Herring <robh@kernel.org> [sboyd@codeaurora.org: Mark stm32f4_pll_div_ops static] Signed-off-by:
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Gabriel Fernandez authored
Creation of dt include file for specific stm32f4 clocks. These specific clocks are not derived from system clock (SYSCLOCK) We should use index 1 to use these clocks in DT. e.g. <&rcc 1 CLK_LSI> Signed-off-by:
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- Dec 13, 2016
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Boris Brezillon authored
best_rate is reported as potentially uninitialized by gcc. Signed-off-by:
Boris Brezillon <boris.brezillon@free-electrons.com> Fixes: 155e8b3b ("clk: bcm: Support rate change propagation on bcm2835 clocks") Reported-by:
Stephen Rothwell <sfr@canb.auug.org.au> Reviewed-by:
Eric Anholt <eric@anholt.net> Signed-off-by:
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- Dec 09, 2016
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Kuninori Morimoto authored
Some driver is using this type of DT bindings for clock (more detail, see ${LINUX}/Documentation/devicetree/bindings/sound/simple-card.txt). sound_soc { ... cpu { clocks = <&xxx>; ... }; codec { clocks = <&xxx>; ... }; }; Current driver in this case uses of_clk_get() for each node, but there is no devm_of_clk_get() today. OTOH, the problem of having devm_of_clk_get() is that it encourages the use of of_clk_get() when clk_get() is more desirable. Thus, this patch adds new devm_get_clk_from_chile() which explicitly reads as get a clock from a child node of this device. By this function, we can also use this type of DT bindings sound_soc { clocks = <&xxx>, <&xxx>; clock-names = "cpu", "codec"; clock-ranges; ... cpu { ... }; codec { ... }; }; Signed-off-by:Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> [sboyd@codeurora.org: Rename subject to clk + add API] Signed-off-by:
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Arvind Yadav authored
Free memory mapping, if probe is not successful. Signed-off-by:
Arvind Yadav <arvind.yadav.cs@gmail.com> Signed-off-by:
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Arvind Yadav authored
Free memory mapping, if of_pll_div_clk_init is not successful. Signed-off-by:
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Arvind Yadav authored
Free memory and memory mapping , if mmp2_clk_init is not successful. Signed-off-by:
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Arvind Yadav authored
Free memory and memory mapping , if pxa910_clk_init is not successful. Signed-off-by:
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Arvind Yadav authored
Free memory, if init is not successful. Signed-off-by:
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Christophe JAILLET authored
It is likely that instead of '1>64', 'q>64' was expected. Moreover, according to datasheet, http://www.ti.com/lit/ds/symlink/cdce925.pdf SCAS847I - JULY 2007 - REVISED OCTOBER 2016 PLL settings limits are: 16 <= q <= 63 So change the upper limit check from 64 to 63. Signed-off-by:
Christophe JAILLET <christophe.jaillet@wanadoo.fr> Signed-off-by:
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Stephen Boyd authored
The broadcom clk driver Kconfig file selects and depends on the COMMON_CLK_IPROC config for different SoC specific drivers. Let's simplify this by always selecting the COMMON_CLK_IPROC config, turning it into a set of library code. We still want to retain the SoC specific options, so we leave those in place. Since we're here we also drop COMMON_CLK dependency because that's implicitly handled by including this file in drivers/clk/Kconfig in the right place and also make CLK_BCM_KONA default to y on the architecture it exists for instead of plain default y. Cc: Florian Fainelli <f.fainelli@gmail.com> Cc: Ray Jui <ray.jui@broadcom.com> Cc: Jon Mason <jonmason@broadcom.com> Signed-off-by: -
Tang Yuantian authored
Acked-by:
Scott Wood <oss@buserror.net> Signed-off-by:
Tang Yuantian <yuantian.tang@nxp.com> [sboyd@codeaurora.org: Sorted list] Signed-off-by:
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Grygorii Strashko authored
Prevent creating clk alias for non existing gmac_gmii_ref_clk_div clock and, this way, eliminate excessive error message during boot: "ti_dt_clocks_register: failed to lookup clock node gmac_gmii_ref_clk_div" Fixes: c097338e ("ARM: dts: dra7: cpsw: fix clocks tree") Signed-off-by:
Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by:
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Boris Brezillon authored
The VEC clock requires needs to be set at exactly 108MHz. Allow rate change propagation on PLLH_AUX to match this requirement wihtout impacting other IPs (PLLH is currently only used by the HDMI encoder, which cannot be enabled when the VEC encoder is enabled). Signed-off-by:
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Boris Brezillon authored
Some peripheral clocks, like the VEC (Video EnCoder) clock need to be set to a precise rate (in our case 108MHz). With the current implementation, where peripheral clocks are not allowed to forward rate change requests to their parents, it is impossible to match this requirement unless the bootloader has configured things correctly, or a specific rate has been assigned through the DT (with the assigned-clk-rates property). Add a new field to struct bcm2835_clock_data to specify which parent clocks accept rate change propagation, and support set rate propagation in bcm2835_clock_determine_rate(). Signed-off-by:
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Boris Brezillon authored
bcm2835_pll_divider_off() is resetting the divider field in the A2W reg to zero when disabling the clock. Make sure we preserve this value by reading the previous a2w_reg value first and ORing the result with A2W_PLL_CHANNEL_DISABLE. Signed-off-by:
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Richard Watts authored
The OMAP36xx DPLL5, driving EHCI USB, can be subject to a long-term frequency drift. The frequency drift magnitude depends on the VCO update rate, which is inversely proportional to the PLL divider. The kernel DPLL configuration code results in a high value for the divider, leading to a long term drift high enough to cause USB transmission errors. In the worst case the USB PHY's ULPI interface can stop responding, breaking USB operation completely. This manifests itself on the Beagleboard xM by the LAN9514 reporting 'Cannot enable port 2. Maybe the cable is bad?' in the kernel log. Errata sprz319 advisory 2.1 documents PLL values that minimize the drift. Use them automatically when DPLL5 is used for USB operation, which we detect based on the requested clock rate. The clock framework will still compute the PLL parameters and resulting rate as usual, but the PLL M and N values will then be overridden. This can result in the effective clock rate being slightly different than the rate cached by the clock framework, but won't cause any adverse effect to USB operation. Signed-off-by:
Richard Watts <rrw@kynesim.co.uk> [Upported from v3.2 to v4.9] Signed-off-by:
Laurent Pinchart <laurent.pinchart@ideasonboard.com> Tested-by:
Ladislav Michl <ladis@linux-mips.org> Signed-off-by:
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- Dec 08, 2016
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Pan Bian authored
Fix bug https://bugzilla.kernel.org/show_bug.cgi?id=188561 . Function wm831x_clkout_is_prepared() returns "true" when it fails to read CLOCK_CONTROL_1. "true" means the device is already prepared. So return "true" on the read failure seems improper. Signed-off-by:
Pan Bian <bianpan2016@163.com> Acked-by:
Charles Keepax <ckeepax@opensource.wolfsonmicro.com> Fixes: f05259a6 ("clk: wm831x: Add initial WM831x clock driver") Signed-off-by:
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Masahiro Yamada authored
Add more data to 64bit SoCs for the cpufreq support. Signed-off-by:
Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by:
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Masahiro Yamada authored
Core support code for CPU frequency changes, which will be used by the generic cpufreq driver. The register view is different from the generic clk-mux; it has a separate status register, and an update bit to load the register setting. Signed-off-by:
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- Dec 07, 2016
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Stephen Boyd authored
Merge tag 'v4.10-rockchip-clk2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next Pull rockchip clk driver updates from Heiko Stuebner: A new clock controller for the rk1108 soc (single-core Cortex-A7+DSP), a fix making sure the cpuclk rate is actually valid, before trying to set it and a copy-paste fix for the rk3399's testclk. * tag 'v4.10-rockchip-clk2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: clk: rockchip: add clock controller for rk1108 dt-bindings: add documentation for rk1108 cru clk: rockchip: add dt-binding header for rk1108 clk: rockchip: fix copy-paste error in rk3399 testclk clk: rockchip: validity should be checked prior to cpu clock rate change
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- Nov 24, 2016
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Sricharan R authored
The venus video ip's internal core blocks are under the control of the firmware and their powerdomains needs to be 'ON' only when used by the firmware. So putting it into hw controlled mode lets this to happen, otherwise the firmware hangs checking for this. Signed-off-by:
Sricharan R <sricharan@codeaurora.org> Signed-off-by:
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Rajendra Nayak authored
Some GDSCs might support a HW control mode, where in the power domain (gdsc) is brought in and out of low power state (while unsued) without any SW assistance, saving power. Such GDSCs can be configured in a HW control mode when powered on until they are explicitly requested to be powered off by software. Signed-off-by:
Rajendra Nayak <rnayak@codeaurora.org> Signed-off-by:
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Stephen Boyd authored
* clk-fixes: clk: bcm: Fix unmet Kconfig dependencies for CLK_BCM_63XX clk: sunxi-ng: enable so-said LDOs for A33 SoC's pll-mipi clock clk: sunxi-ng: sun6i-a31: Enable PLL-MIPI LDOs when ungating it
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Florian Fainelli authored
With commit f4e87150 ("clk: iproc: Make clocks visible options"), COMMON_CLK_IPROC gained a dependency on ARCH_BCM_IPROC, yet CLK_BCM_63XX also selects that option, this causes the following Kconfig warning: warning: (CLK_BCM_63XX) selects COMMON_CLK_IPROC which has unmet direct dependencies ((ARCH_BCM_IPROC || COMPILE_TEST) && COMMON_CLK) Fix this by adding proper depends for COMMON_CLK_IPROC Fixes: f4e87150 ("clk: iproc: Make clocks visible options") Signed-off-by:
Florian Fainelli <f.fainelli@gmail.com> Reviewed-by:
Ray Jui <ray.jui@broadcom.com> [sboyd@codeaurora.org: Drop default part as it's redundant] Signed-off-by:
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Icenowy Zheng authored
In the user manual of A33 SoC, the bit 22 and 23 of pll-mipi control register is called "LDO{1,2}_EN", and according to the BSP source code from Allwinner [1], the LDOs are enabled during the clock's enabling process. The clock failed to generate output if the two LDOs are not enabled. Add the two bits to the clock's gate bits, so that the LDOs are enabled when the PLL is enabled. [1] https://github.com/allwinner-zh/linux-3.4-sunxi/blob/master/drivers/clk/sunxi/clk-sun8iw5.c#L429 Fixes: d05c748b ("clk: sunxi-ng: Add A33 CCU support") Signed-off-by:Icenowy Zheng <icenowy@aosc.xyz> Acked-by:
Chen-Yu Tsai <wens@csie.org> Signed-off-by:
Maxime Ripard <maxime.ripard@free-electrons.com>
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Boris Brezillon authored
There is no fixed divider on pllh_aux. Signed-off-by:
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Georgi Djakov authored
Fix the clk_hw references to the actual clocks and add a xlate function to return the hw pointers from the already existing static array. Reported-by:
Michael Scott <michael.scott@linaro.org> Signed-off-by:
Georgi Djakov <georgi.djakov@linaro.org> Signed-off-by:
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Georgi Djakov authored
Fix the clk_hw references to the actual clocks and add a xlate function to return the hw pointers from the already existing static array. Reported-by:
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Rajendra Nayak authored
The sdcc driver for msm8996/msm8916/msm8974/msm8994 and apq8084 expects a clk_set_rate() on the sdcc rcg clk to set a floor value of supported clk rate closest to the requested rate, by looking up the frequency table. So move all the sdcc rcgs on all these platforms to use the newly introduced clk_rcg2_floor_ops Signed-off-by:
Ritesh Harjani <riteshh@codeaurora.org> Signed-off-by:
Jeremy McNicoll <jeremymc@redhat.com> Signed-off-by:
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Rajendra Nayak authored
The default behaviour with clk_rcg2_ops is for the clk_round_rate()/clk_set_rate() to return/set a ceil clock rate closest to the requested rate by looking up the corresponding frequency table. However, we do have some instances (mainly sdcc on various platforms) of clients expecting a clk_set_rate() to set a floor value instead. Add a new clk_rcg2_floor_ops to handle this for such specific rcg instances Signed-off-by:
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- Nov 22, 2016
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git://linuxtv.org/snawrocki/samsungStephen Boyd authored
Pull Exynos5433 SoC updates from Sylwester Nawrocki: - addition of missing documentation and DT properties for the CMU_AUD block source clocks, - correction of CMU_FSYS parent clock definition, - marking as critical clocks which have to be enabled in order to access control registers of child CMUs. * tag 'clk-v4.10-exynos5433' of git://linuxtv.org/snawrocki/samsung: clk: exynos5433: Mark some clocks as critical clk: exynos5433: Add documentation for the audio block parent clocks clk: exynos5433: Fix parent clocks for FSYS block
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Chen-Yu Tsai authored
The PLL-MIPI clock is somewhat special as it has its own LDOs which need to be turned on for this PLL to actually work and output a clock signal. Add the 2 LDO enable bits to the gate bits. This fixes issues with the TCON not sending vblank interrupts when the tcon and dot clock are indirectly clocked from the PLL-MIPI clock. Fixes: c6e6c96d ("clk: sunxi-ng: Add A31/A31s clocks") Signed-off-by:
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- Nov 18, 2016
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Marek Szyprowski authored
Some parent clocks of the Exynos5433 CMUs must be always enabled to access any register in the given CMU or devices connected to it. For the time being, until a proper solution based on runtime PM is applied, mark those clocks as critical (instead of ignore unused) to prevent disabling them. Reported-by:
Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by:
Marek Szyprowski <m.szyprowski@samsung.com> Reviewed-by:
Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by:
Sylwester Nawrocki <s.nawrocki@samsung.com>
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Stephen Boyd authored
Merge tag 'clk-renesas-for-v4.10-tag3' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-next Pull more clk driver updates from Geert Uytterhoeven: - CSI2 and VIN clocks for R-Car M3-W, - Clock drivers for new RZ/G1M and RZ/G1E SoCs, - Minor bug fix for R-Car H3. * tag 'clk-renesas-for-v4.10-tag3' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers: clk: renesas: cpg-mssr: Add R8A7745 support clk: renesas: cpg-mssr: Add R8A7743 support clk: renesas: cpg-mssr: Add common R-Car Gen2 support clk: renesas: r8a7795: Fix HDMI parent clock clk: renesas: r8a7796: Add VIN clocks clk: renesas: r8a7796: Add CSI2 clocks
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