- Feb 23, 2024
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Abel Vesa authored
Document the MDSS hardware found on the Qualcomm X1E80100 platform. Reviewed-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by:
Abel Vesa <abel.vesa@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/579074/ Link: https://lore.kernel.org/r/20240220-x1e80100-display-v4-2-971afd9de861@linaro.org Signed-off-by:
Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
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Abel Vesa authored
Document the DPU for Qualcomm X1E80100 platform in the SM8650 schema, as they are similar. Reviewed-by:
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- Feb 19, 2024
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Dmitry Baryshkov authored
Since the commit b962a120 ("drm/atomic: integrate modeset lock with private objects") the DRM framework no longer requires the external lock for private objects. Drop the lock, letting the DRM to manage private object locking. Signed-off-by:
Abhinav Kumar <quic_abhinavk@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/570183/ Link: https://lore.kernel.org/r/20231203000532.1290480-6-dmitry.baryshkov@linaro.org
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Dmitry Baryshkov authored
The Shared Memory Pool (SMP) state is a part of the MDP5's private object state. Use existing infrastructure, atomic_print_state() callback, to dump SMP state (which also makes it included into debugfs/dri/N/state). This allows us to drop the custom debugfs file too. Signed-off-by:
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Dmitry Baryshkov authored
Since the commit b962a120 ("drm/atomic: integrate modeset lock with private objects") the DRM framework no longer requires the external lock for private objects. Drop the lock, letting the DRM to manage private object locking. Signed-off-by:
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Dmitry Baryshkov authored
Add calls to finalise global state object and corresponding lock. Fixes: de3916c7 ("drm/msm/dpu: Track resources in global state") Signed-off-by:
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Dmitry Baryshkov authored
Bring in hardware support for the SDM660 and SDM630 platforms, which belong to the same DPU generation as MSM8998. Note, by default these platforms are still handled by the MDP5 driver unless the `msm.prefer_mdp5=false' parameter is provided. Co-developed-by:
Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by:
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Dmitry Baryshkov authored
For some of the platforms (e.g. SDM660, SDM630, MSM8996, etc.) it is possible to support this platform via the DPU driver (e.g. to provide support for DP, multirect, etc). Add a modparam to be able to switch between these two drivers. All platforms supported by both drivers are by default handled by the MDP5 driver. To let them be handled by the DPU driver pass the `msm.prefer_mdp5=false` kernel param. Reviewed-by:
Stephen Boyd <swboyd@chromium.org> Reviewed-by:
Carl Vanderlip <quic_carlv@quicinc.com> Reviewed-by:
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Dmitry Baryshkov authored
Existing MDP5 devices have slightly different bindings. The main register region is called `mdp_phys' instead of `mdp'. Also vbif register regions are a part of the parent, MDSS device. Add support for handling this binding differences. Signed-off-by:
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Dmitry Baryshkov authored
Older (mdp5) platforms do not use per-SoC compatible strings. Instead they use a single compat entry 'qcom,mdss'. To facilitate migrating these platforms to the DPU driver provide a way to generate the MDSS / UBWC data at runtime, when the DPU driver asks for it. It is not possible to generate this data structure at the probe time, since some platforms might not have MDP_CLK enabled, which makes reading HW_REV register useless and prone to possible crashes. Signed-off-by:
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Colin Ian King authored
There is a spelling mistake in a drm_dbg_dp message. Fix it. Signed-off-by:
Colin Ian King <colin.i.king@gmail.com> Reviewed-by:
Neil Armstrong <neil.armstrong@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/577760/ Link: https://lore.kernel.org/r/20240212091639.2397424-1-colin.i.king@gmail.com Signed-off-by:
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- Feb 12, 2024
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Dmitry Baryshkov authored
Provide actual documentation for the pclk and hdisplay calculations in the case of DSC compression being used. Signed-off-by:
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Dmitry Baryshkov authored
Writeback was the last user of dpu_encoder_phys_ops's atomic_check() callback. As the code was moved to the dpu_writeback.c, the callback becomes unused. Drop it now. Reviewed-by:
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Dmitry Baryshkov authored
dpu_encoder_phys_wb is the only user of encoder's atomic_check callback. Move corresponding checks to drm_writeback_connector's implementation and drop the dpu_encoder_phys_wb_atomic_check() function. Signed-off-by:
Paloma Arellano <quic_parellan@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/577524/ Link: https://lore.kernel.org/r/20240208-fd_remove_phys_ops_atomic_mode_set-v4-4-caf5dcd125c0@linaro.org
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Dmitry Baryshkov authored
The atomic_mode_set() callback only sets the phys_enc's IRQ data. As the INTF and WB are statically allocated to each encoder/phys_enc, drop the atomic_mode_set callback and set the IRQs during encoder init. For the CMD panel usecase some of IRQ indexes depend on the selected resources. Move setting them to the irq_enable() callback. Reviewed-by:
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Dmitry Baryshkov authored
Follow the _dpu_encoder_irq_control() change and split the _dpu_encoder_resource_control_helper() into enable and disable parts. Reviewed-by:
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Dmitry Baryshkov authored
The single helper for both enable and disable cases is too complicated, especially if we start adding more code to these helpers. Split it into irq_enable and irq_disable cases. Reviewed-by:
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Marijn Suijten authored
When the topology calls for two interfaces on the current fixed topology of 2 DSC blocks, or uses 1 DSC block for a single interface (e.g. SC7280 with only one DSC block), there should be no merging of DSC output. This is already represented by the return value of dpu_encoder_use_dsc_merge(), but not yet used to correctly configure this flag. Fixes: 58dca981 ("drm/msm/disp/dpu1: Add support for DSC in encoder") Signed-off-by:
Marijn Suijten <marijn.suijten@somainline.org> Reviewed-by:
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Marijn Suijten authored
drm_mipi_dsi.h already provides a conversion function from MIPI_DSI_FMT_ to bpp, named mipi_dsi_pixel_format_to_bpp(). Signed-off-by:
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Rob Herring authored
In order to check schemas for missing additionalProperties or unevaluatedProperties, cases allowing extra properties must be explicit. Signed-off-by:
Rob Herring <robh@kernel.org> Reviewed-by:
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Abhinav Kumar authored
Currently INTF_CFG2_DATA_HCTL_EN is coupled with the enablement of widebus but this is incorrect because we should be enabling this bit independent of widebus except for cases where compression is enabled in one pixel per clock mode. Fix this by making the condition checks more explicit and enabling INTF_CFG2_DATA_HCTL_EN for all other cases when supported by DPU. Fixes: 3309a756 ("drm/msm/dpu: revise timing engine programming to support widebus feature") Suggested-by:
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Dmitry Baryshkov authored
Finally drop separate "parsing" submodule. There is no need in it anymore. All submodules handle DT properties directly rather than passing them via the separate structure pointer. Signed-off-by:
Konrad Dybcio <konrad.dybcio@linaro.org> Tested-by:
Kuogee Hsieh <quic_khsieh@quicinc.com> Reviewed-by:
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Dmitry Baryshkov authored
Remove two levels of indirection and fetch next bridge directly in dp_display_probe_tail(). Signed-off-by:
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Dmitry Baryshkov authored
Instead of passing link properties through the separate struct, parse them directly in the dp_panel. Signed-off-by:
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Dmitry Baryshkov authored
Rather than parsing the I/O addresses from dp_parser and then passing them via a struct pointer to dp_catalog, handle I/O region parsing in dp_catalog and drop it from dp_parser. Signed-off-by:
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Dmitry Baryshkov authored
There is little point in going trough dp_parser->io indirection each time the driver needs to access the PHY. Store the pointer directly in dp_ctrl_private. Signed-off-by:
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Dmitry Baryshkov authored
Inline dp_catalog_aux_update_cfg() and call phy_calibrate() from dp_aux functions directly. Signed-off-by:
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Dmitry Baryshkov authored
There is little point in sharing phy configuration structure between several modules. Move it to dp_ctrl, which becomes the only submodule re-configuring the PHY. Signed-off-by:
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Dmitry Baryshkov authored
Split the dp_ctrl_clk_enable() beast into four functions, each of them doing just a single item: enabling or disabling core or link clocks. This allows us to cleanup the dss_module_power structure and makes several dp_ctrl functions return void. Signed-off-by:
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Dmitry Baryshkov authored
All supported platforms use the same clocks configuration. Instead of parsing names from DT in a pretty complex manner, use the static configuration. If at some point newer (or older) platforms have different clock configuration, this clock config can be moved to the device data. Signed-off-by:
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Dmitry Baryshkov authored
There is only a single DP_STREAM_PM clock, stream_pixel. Instead of using a separate dss_module_power instance for this single clock, handle this clock directly. This allows us to drop several wrapping functions. Signed-off-by:
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Dmitry Baryshkov authored
The dp_power submodule is limited to handling the clocks only following previous cleanups. Fold it into the dp_ctrl submodule, removing one unnecessary level of indirection. Signed-off-by:
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Dmitry Baryshkov authored
In preparation to cleanup of the dp_power module, inline dp_power_init() and dp_power_deinit() functions, which are now just turning the clocks on and off. Reviewed-by:
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Dmitry Baryshkov authored
It makes little sense to split the submodule get and actual DT parsing. Call dp_parser_parse() directly from dp_parser_get(), so that the parser data is fully initialised once it is returned to the caller. Reviewed-by:
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Dmitry Baryshkov authored
Drop unused and obsolete fields from struct dp_power_private. Reviewed-by:
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Dmitry Baryshkov authored
Drop several unused and obsolete definitions from the dp_parser module. Signed-off-by:
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Adam Skladowski authored
During conversion 28nm-hpm-fam-b compat got lost, add it. Signed-off-by:
Adam Skladowski <a39.skl@gmail.com> Fixes: f7d46c5e ("dt-bindings: display/msm: split qcom, mdss bindings") Acked-by:
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Adam Skladowski authored
When all dsi-ctrl compats were added msm8976 was missed, include it too. Signed-off-by:
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Kuogee Hsieh authored
mdss_dp_test_bit_depth_to_bpc() can be replace by mdss_dp_test_bit_depth_to_bpp() / 3. Hence remove it. Signed-off-by:
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Kuogee Hsieh authored
At DSC V1.1 DCE (Display Compression Engine) contains a DSC encoder. However, at DSC V1.2 DCE consists of two DSC encoders, one has an odd index and another one has an even index. Each encoder can work independently. But only two DSC encoders from same DCE can be paired to work together to support DSC merge mode at DSC V1.2. For DSC V1.1 two consecutive DSC encoders (start with even index) have to be paired to support DSC merge mode. In addition, the DSC with even index have to be mapped to even PINGPONG index and DSC with odd index have to be mapped to odd PINGPONG index at its data path in regardless of DSC V1.1 or V1.2. This patch improves DSC allocation mechanism with consideration of those factors. Changes in V6: -- rename _dpu_rm_reserve_dsc_single to _dpu_rm_dsc_alloc -- rename _dpu_rm_reserve_dsc_pair to _dpu_rm_dsc_alloc_pair -- pass global_state to _dpu_rm_pingpong_next_index() -- remove pp_max -- fix for loop condition check at _dpu_rm_dsc_alloc() Changes in V5: -- delete dsc_id[] -- update to global_state->dsc_to_enc_id[] directly -- replace ndx with idx -- fix indentation at function declaration -- only one for loop at _dpu_rm_reserve_dsc_single() Changes in V4: -- rework commit message -- use reserved_by_other() -- add _dpu_rm_pingpong_next_index() -- revise _dpu_rm_pingpong_dsc_check() Changes in V3: -- add dpu_rm_pingpong_dsc_check() -- for pair allocation use i += 2 at for loop Changes in V2: -- split _dpu_rm_reserve_dsc() into _dpu_rm_reserve_dsc_single() and _dpu_rm_reserve_dsc_pair() Fixes: f2803ee9 ("drm/msm/disp/dpu1: Add DSC support in RM") Signed-off-by:
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