- Jun 22, 2019
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Harry Wentland authored
Add DCN2 resource definition and HW Sequencer changes. Signed-off-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Harry Wentland authored
Add support to program DCN2 VMID (Virtual Memory Support) Signed-off-by:
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Harry Wentland authored
Add support to program DCN2 cursor (IPP) Signed-off-by:
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Harry Wentland authored
Add support to program the DCN2 DWB (Display Writeback) HW Blocks: +--------++------+ +----------+ | HUBBUB || HUBP | <-- | MMHUBBUB | +--------++------+ +----------+ | ^ v | +--------+ +--------+ | DPP | | DWB | +--------+ +--------+ | v ^ +--------+ | | MPC | | +--------+ | | | v | +-------+ | | OPP | | +-------+ | | | v | +--------+ / | OPTC | -------------- +--------+ | v +--------+ +--------+ | DIO | | DCCG | +--------+ +--------+ Signed-off-by: -
Harry Wentland authored
Add support to program the DCN2 MMHUBBUB (Multimedia HUB interface) HW Blocks: +--------++------+ +----------+ | HUBBUB || HUBP | <-- | MMHUBBUB | +--------++------+ +----------+ | v +--------+ | DPP | +--------+ | v +--------+ | MPC | +--------+ | v +-------+ | OPP | +-------+ | v +--------+ | OPTC | +--------+ | v +--------+ +--------+ | DIO | | DCCG | +--------+ +--------+ Signed-off-by: -
Harry Wentland authored
Add support to program the DCN2 HUBP (Display to data fabric interface pipe) and HUBBUB (DCN memory HUB interface) HW Blocks: +--------++------+ | HUBBUB || HUBP | +--------++------+ | v +--------+ | DPP | +--------+ | v +--------+ | MPC | +--------+ | v +-------+ | OPP | +-------+ | v +--------+ | OPTC | +--------+ | v +--------+ +--------+ | DIO | | DCCG | +--------+ +--------+ Signed-off-by: -
Harry Wentland authored
Add support to program the DCN2 DPP (Multiple pipe and plane combine) HW Blocks: +--------+ | DPP | +--------+ | v +--------+ | MPC | +--------+ | v +-------+ | OPP | +-------+ | v +--------+ | OPTC | +--------+ | v +--------+ +--------+ | DIO | | DCCG | +--------+ +--------+ Signed-off-by: -
Harry Wentland authored
Add support to program the DCN2 MPC (Multiple pipe and plane combine) HW Blocks: +--------+ | MPC | +--------+ | v +-------+ | OPP | +-------+ | v +--------+ | OPTC | +--------+ | v +--------+ +--------+ | DIO | | DCCG | +--------+ +--------+ Signed-off-by: -
Harry Wentland authored
Add support to program the DCN2 OPP (Output Plane Processing) HW Blocks: +-------+ | OPP | +-------+ | v +--------+ | OPTC | +--------+ | v +--------+ +--------+ | DIO | | DCCG | +--------+ +--------+ Signed-off-by: -
Harry Wentland authored
Add support for programming the DCN2 OPTC (Output Timing Controller) HW Blocks: +--------+ | OPTC | +--------+ | v +--------+ +--------+ | DIO | | DCCG | +--------+ +--------+ Signed-off-by: -
Harry Wentland authored
Adds support for handling of clocking relevant to the DCN2 block, including programming of the DCCG (Display Controller Clock Generator) block: HW Blocks: +--------+ +--------+ | DIO | | DCCG | +--------+ +--------+ Signed-off-by: -
Harry Wentland authored
Add support for the DIO (Display IO) block of DCN2, which entails our stream and link encoders. HW Blocks: +--------+ | DIO | +--------+ Signed-off-by: -
Harry Wentland authored
Update DML (Display Mode Lib) to support DCN2 Signed-off-by:
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Harry Wentland authored
Add support to program DCN2 IRQ handling Signed-off-by:
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Harry Wentland authored
Handle BIOS parsing for DCN2 Signed-off-by:
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Harry Wentland authored
Adding support to program GPIO HW block of DCN2 Signed-off-by:
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Harry Wentland authored
Adding support to program DCN2 AUX and I2C HW. Signed-off-by:
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Harry Wentland authored
DCN2.0 (Display Core Next) is the display block in Navi10. Signed-off-by:
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Xiaojie Yuan authored
since it's firmware. Signed-off-by:
Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by:
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Leo Li authored
DC needs to include the soc bounding box when initializing HW resources. Including amdgpu_ucode.h directly will cause warnings, since amdgpu.h is required to define amdgpu_device. The solution here is to split the bounding box structs into a different header, then include it in both amdgpu_ucode.h, and relevant DC HW resource files. Signed-off-by:
Leo Li <sunpeng.li@amd.com> Signed-off-by:
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Harry Wentland authored
[WHY] We don't want to expose sensitive ASIC information before ASIC release. [HOW] Encode the soc_bounding_box in the gpu_info FW (for Linux) and read it at driver load. v2: fix warning when CONFIG_DRM_AMD_DC_DCN2_0 is not set (Alex) Signed-off-by:
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hersen wu authored
when dc update clocks via smu, smu needs to know how many displays active. this interface is for dc notify number of active displays to smu. Signed-off-by:
hersen wu <hersenxs.wu@amd.com> Reviewed-by:
Huang Rui <ray.huang@amd.com> Acked-by:
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hersen wu authored
when dc set mode or color format in frame buffer change, it may request clock changes, like dispclk, dcfclk, uclk. after smu get clock requests, smu will make decision. Signed-off-by:
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Hawking Zhang authored
was missed before. Signed-off-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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Marek Olšák authored
Proper size is 0. v2: squash in whitespace fixes (Ernst Sjöstrand) Signed-off-by:
Marek Olšák <marek.olsak@amd.com> Reviewed-by:
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Kevin Wang authored
the PPSMC_MSG_SetFanTemperatureTarget is not support on navi10 Signed-off-by:
Kevin Wang <kevin1.wang@amd.com> Reviewed-by:
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Jack Xiao authored
It would hit SMU fw bug without BACO enablement when audio driver put audio device to D3 state. Before the bug in SMU fw get fixed, enable BACO feature as WAR. Signed-off-by:
Jack Xiao <Jack.Xiao@amd.com> Acked-by:
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Kevin Wang authored
the uclk dpm feature is not work well on all navi10 asic, use pp feature mask module parameter to control it. Signed-off-by:
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tiancyin authored
Reviewed-by:
tiancyin <tianci.yin@amd.com> Signed-off-by:
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tiancyin authored
Include the interface version as well. Signed-off-by:
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Alex Deucher authored
Fix UTCL1_CGTT_CLK_CTRL Signed-off-by: -
Alex Deucher authored
Use the SMU_* variant so we look up the correct index. Signed-off-by: -
Leo Liu authored
This is default mode for VCN2.x now Signed-off-by:
Leo Liu <leo.liu@amd.com> Reviewed-by:
James Zhu <James.Zhu@amd.com> Signed-off-by:
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Leo Liu authored
SRAM will be programmed by PSP Signed-off-by:
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Leo Liu authored
This will be used later for indirect SRAM mode Signed-off-by:
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Jack Xiao authored
SMU FW has bug that it would cause hung when both fw dstate and gfxoff are enabled at the same time. Signed-off-by:
Kenneth Feng <kenneth.feng@amd.com> Signed-off-by:
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Jack Xiao authored
update the smu11_driver_if_navi10.h since navi10 smu fw update to 42.23 Signed-off-by:
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Jack Xiao authored
PSP leverages the existing fw loading function for vcn updating sram. Signed-off-by:
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Jack Xiao authored
Convert ucode id to the corresponding psp ucode id. Signed-off-by:
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Jack Xiao authored
Add VCN RAM ucode id in corresponding to psp ucode id. Signed-off-by:
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