1. Dec 06, 2022
    • ye xingchen's avatar
      cpufreq: stats: Convert to use sysfs_emit_at() API · 7ed40bcf
      ye xingchen authored
      
      
      Follow the advice of the Documentation/filesystems/sysfs.rst and show()
      should only use sysfs_emit() or sysfs_emit_at() when formatting the
      value to be returned to user space.
      
      Signed-off-by: default avatarye xingchen <ye.xingchen@zte.com.cn>
      Acked-by: default avatarViresh Kumar <viresh.kumar@linaro.org>
      Signed-off-by: default avatarRafael J. Wysocki <rafael.j.wysocki@intel.com>
      7ed40bcf
    • Stuart Hayes's avatar
      cpufreq: ACPI: Only set boost MSRs on supported CPUs · 44204632
      Stuart Hayes authored
      Stop trying to set boost MSRs on CPUs that don't support boost.
      
      This corrects a bug in the recent patch "Defer setting boost MSRs".
      
      Fixes: 13fdbc8b
      
       ("cpufreq: ACPI: Defer setting boost MSRs")
      Signed-off-by: default avatarStuart Hayes <stuart.w.hayes@gmail.com>
      Reported-by: default avatarBorislav Petkov (AMD) <bp@alien8.de>
      Tested-by: default avatarBorislav Petkov (AMD) <bp@alien8.de>
      Signed-off-by: default avatarRafael J. Wysocki <rafael.j.wysocki@intel.com>
      44204632
    • Rafael J. Wysocki's avatar
      Merge tag 'cpufreq-arm-updates-6.2' of git://git.kernel.org/pub/scm/linux/kernel/git/vireshk/pm · edeba49e
      Rafael J. Wysocki authored
      Pull cpufreq ARM updates for 6.2 from Viresh Kumar:
      
      "- Generalize of_perf_domain_get_sharing_cpumask phandle format (Hector
         Martin).
      
       - New cpufreq driver for Apple SoC CPU P-states (Hector Martin).
      
       - Lots of Qualcomm cpufreq driver updates, that include CPU clock
         provider support, generic cleanups or reorganization, fixed a
         potential memleak and the return value of cpufreq_driver->get()
         (Manivannan Sadhasivam, and Chen Hui).
      
       - Few updates to Qualcomm cpufreq driver's DT bindings, that include
         support for CPU clock provider, fixing missing cache related
         properties, and support for QDU1000/QRU1000 (Manivannan Sadhasivam,
         Rob Herring, and Melody Olvera).
      
       - Add support for ti,am625 SoC and enable build of ti-cpufreq for
         ARCH_K3 (Dave Gerlach, and Vibhore Vardhan).
      
       - tegra186: Use flexible array to simplify memory allocation (Christophe
         JAILLET)."
      
      * tag 'cpufreq-arm-updates-6.2' of git://git.kernel.org/pub/scm/linux/kernel/git/vireshk/pm:
        dt-bindings: cpufreq: cpufreq-qcom-hw: Add QDU1000/QRU1000 cpufreq
        cpufreq: tegra186: Use flexible array to simplify memory allocation
        cpufreq: apple-soc: Add new driver to control Apple SoC CPU P-states
        cpufreq: qcom-hw: Add CPU clock provider support
        dt-bindings: cpufreq: cpufreq-qcom-hw: Add cpufreq clock provider
        cpufreq: qcom-hw: Fix the frequency returned by cpufreq_driver->get()
        cpufreq: qcom-hw: Fix memory leak in qcom_cpufreq_hw_read_lut()
        arm64: dts: ti: k3-am625-sk: Add 1.4GHz OPP
        cpufreq: ti: Enable ti-cpufreq for ARCH_K3
        arm64: dts: ti: k3-am625: Introduce operating-points table
        cpufreq: dt-platdev: Blacklist ti,am625 SoC
        cpufreq: ti-cpufreq: Add support for AM625
        dt-bindings: cpufreq: qcom: Add missing cache related properties
        cpufreq: qcom-hw: Move soc_data to struct qcom_cpufreq
        cpufreq: qcom-hw: Use cached dev pointer in probe()
        cpufreq: qcom-hw: Allocate qcom_cpufreq_data during probe
        cpufreq: qcom-hw: Remove un-necessary cpumask_empty() check
        cpufreq: Generalize of_perf_domain_get_sharing_cpumask phandle format
      edeba49e
  2. Dec 01, 2022
  3. Nov 30, 2022
    • Hector Martin's avatar
      cpufreq: apple-soc: Add new driver to control Apple SoC CPU P-states · 6286bbb4
      Hector Martin authored
      
      
      This driver implements CPU frequency scaling for Apple Silicon SoCs,
      including M1 (t8103), M1 Max/Pro/Ultra (t600x), and M2 (t8112).
      
      Each CPU cluster has its own register set, and frequency management is
      fully automated by the hardware; the driver only has to write one
      register. There is boost frequency support, but the hardware will only
      allow their use if only a subset of cores in a cluster are in
      non-deep-idle. Since we don't support deep idle yet, these frequencies
      are not achievable, but the driver supports them. They will remain
      disabled in the device tree until deep idle is implemented, to avoid
      confusing users.
      
      This driver does not yet implement the memory controller performance
      state tuning that usually accompanies higher CPU p-states. This will be
      done in a future patch.
      
      Acked-by: default avatarMarc Zyngier <maz@kernel.org>
      Signed-off-by: default avatarHector Martin <marcan@marcan.st>
      Signed-off-by: default avatarViresh Kumar <viresh.kumar@linaro.org>
      6286bbb4
  4. Nov 28, 2022
  5. Nov 24, 2022
    • Manivannan Sadhasivam's avatar
      cpufreq: qcom-hw: Add CPU clock provider support · 4370232c
      Manivannan Sadhasivam authored
      
      
      Qcom CPUFreq hardware (EPSS/OSM) controls clock and voltage to the CPU
      cores. But this relationship is not represented with the clk framework
      so far.
      
      So, let's make the qcom-cpufreq-hw driver a clock provider. This makes the
      clock producer/consumer relationship cleaner and is also useful for CPU
      related frameworks like OPP to know the frequency at which the CPUs are
      running.
      
      The clock frequency provided by the driver is for each frequency domain.
      We cannot get the frequency of each CPU core because, not all platforms
      support per-core DCVS feature.
      
      Also the frequency supplied by the driver is the actual frequency that
      comes out of the EPSS/OSM block after the DCVS operation. This frequency is
      not same as what the CPUFreq framework has set but it is the one that gets
      supplied to the CPUs after throttling by LMh.
      
      Signed-off-by: default avatarManivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
      [ Xiu: Fixed memleak. ]
      Signed-off-by: default avatarXiu Jianfeng <xiujianfeng@huawei.com>
      Signed-off-by: default avatarViresh Kumar <viresh.kumar@linaro.org>
      4370232c
  6. Nov 23, 2022
  7. Nov 21, 2022
  8. Nov 20, 2022
  9. Nov 19, 2022