- Dec 16, 2023
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Stephan Gerhold authored
The blsp_dma controller is shared between the different subsystems, which is why it is already initialized by the firmware. We should not reinitialize it from Linux to avoid potential other users of the DMA engine to misbehave. In mainline this can be described using the "qcom,controlled-remotely" property. In the downstream/vendor kernel from Qualcomm there is an opposite "qcom,managed-locally" property. This property is *not* set for the qcom,sps-dma@7884000 [1] so adding "qcom,controlled-remotely" upstream matches the behavior of the downstream/vendor kernel. Adding this seems to fix some weird issues with UART where both input/output becomes garbled with certain obscure firmware versions on some devices. [1]: https://git.codelinaro.org/clo/la/kernel/msm-3.10/-/blob/LA.BR.1.2.9.1-02310-8x16.0/arch/arm/boot/dts/qcom/msm8916.dtsi#L1466-1472 Cc: stable@vger.kernel.org # 6.5 Fixes: a0e5fb10 ("arm64: dts: qcom: Add msm8916 BLSP device nodes") Signed-off-by:
Stephan Gerhold <stephan@gerhold.net> Reviewed-by:
Bryan O'Donoghue <bryan.odonoghue@linaro.org> Link: https://lore.kernel.org/r/20231204-msm8916-blsp-dma-remote-v1-1-3e49c8838c8d@gerhold.net Signed-off-by:
Bjorn Andersson <andersson@kernel.org>
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Stephan Gerhold authored
Looks like not all firmware versions used for MSM8939 program the timer frequency for both broadcast/MMIO timers, causing a WARNING at runtime: WARNING: CPU: 0 PID: 0 at kernel/time/clockevents.c:38 cev_delta2ns+0x74/0x90 pc : cev_delta2ns+0x74/0x90 lr : clockevents_config.part.0+0x64/0x8c Call trace: cev_delta2ns+0x74/0x90 clockevents_config_and_register+0x20/0x34 arch_timer_mem_of_init+0x374/0x534 timer_probe+0x88/0x110 time_init+0x14/0x4c start_kernel+0x2c0/0x640 Unfortunately there is no way to fix the firmware on most of these devices since it's proprietary and signed. As a workaround, specify the clock-frequency explicitly in the DT to fix the warning. Fixes: 61550c6c ("arm64: dts: qcom: Add msm8939 SoC") Reported-by:
Vincent Knecht <vincent.knecht@mailoo.org> Signed-off-by:
Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20231204-msm8939-timer-v1-1-a2486c625786@gerhold.net Signed-off-by:
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Stephan Gerhold authored
Add the missing vio-supply to all usages of the AW2013 LED controller to ensure that the regulator needed for pull-up of the interrupt and I2C lines is really turned on. While this seems to have worked fine so far some of these regulators are not guaranteed to be always-on. For example, pm8916_l6 is typically turned off together with the display if there aren't any other devices (e.g. sensors) keeping it always-on. Cc: stable@vger.kernel.org # 6.6 Signed-off-by:
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Chukun Pan authored
Add node to support the QUP5 SPI controller inside of IPQ6018. Some routers use this bus to connect SPI TPM chips. Signed-off-by:
Chukun Pan <amadeus@jmu.edu.cn> Link: https://lore.kernel.org/r/20231203154003.532765-1-amadeus@jmu.edu.cn Signed-off-by:
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Chukun Pan authored
Add node to support all the QUP UART node controller inside of IPQ6018. Some routers use these bus to connect Bluetooth chips. Signed-off-by:
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Konrad Dybcio authored
Enable the remote processors and tighten up the regulators to enable Wi-Fi functionality on the RB2. For reference, the hw/sw identifies as: qmi chip_id 0x150 chip_family 0x4002 board_id 0xff soc_id 0x40670000 qmi fw_version 0x337302d3 fw_build_timestamp 2023-01-06 01:50 fw_build_id QC_IMAGE_VERSION_STRING=WLAN.HL.3.3.7.c2-00723-QCAHLSWMTPLZ-1 wcn3990 hw1.0 target 0x00000008 chip_id 0x00000000 sub 0000:0000 kconfig debug 0 debugfs 0 tracing 0 dfs 0 testmode 0 firmware ver api 5 features wowlan,mgmt-tx-by-reference,non-bmi crc32 b3d4b790 htt-ver 3.114 wmi-op 4 htt-op 3 cal file max-sta 32 raw 0 hwcrypto 1 Signed-off-by:
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- Dec 09, 2023
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Luca Weiss authored
Now that the WPSS remoteproc is enabled, enable wifi so we can use it. Reviewed-by:
Luca Weiss <luca.weiss@fairphone.com> Link: https://lore.kernel.org/r/20231208-sc7280-remoteprocs-v3-11-6aa394d33edf@fairphone.com Signed-off-by:
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Luca Weiss authored
Enable the ADSP, CDSP, MPSS and WPSS that are found on the SoC. Reviewed-by:
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Luca Weiss authored
Add the node for the ADSP found on the SC7280 SoC, using standard Qualcomm firmware. Remove the reserved-memory node from sc7280-chrome-common since CDSP is currently not used there. Acked-by:
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Luca Weiss authored
Add the node for the ADSP found on the SC7280 SoC, using standard Qualcomm firmware. Acked-by:
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Luca Weiss authored
The wpss-pil driver wants to manage too many resources that cannot be touched with standard Qualcomm firmware. Use the compatible from the PAS driver and move the ChromeOS-specific bits to sc7280-chrome-common.dtsi. Signed-off-by:
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Luca Weiss authored
Enable the UFS phy and controller so that we can access the internal storage of the phone. At the same time we need to bump the minimum voltage used for UFS VCC, otherwise it doesn't initialize properly. The 2.952V is taken from the vcc-voltage-level property downstream. See also the following link for more information about the VCCQ/VCCQ2: https://gerrit-public.fairphone.software/plugins/gitiles/kernel/msm-extra/devicetree/+/1590a3739e7dc29d2597307881553236d492f188/fp5/yupik-idp-pm7250b.dtsi#207 Signed-off-by:
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Luca Weiss authored
The dtbs_check really doesn't like having memory without reg set. The base address depends on the amount of RAM you have: <= 2.00 GiB RAM: 0x80000000 = 3.00 GiB RAM: 0x40000000 = 3.75 GiB RAM: 0x10000000 (more does not fit into the 32-bit physical address space) So, let's pick one of the values, 0x10000000 which is used on devices with 3.75 GiB RAM. Since the bootloader will update it to what's present on the device it doesn't matter too much. Signed-off-by:
Luca Weiss <luca@z3ntu.xyz> Link: https://lore.kernel.org/r/20231125-msm8953-misc-fixes-v2-1-df86655841d9@z3ntu.xyz Signed-off-by:
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Nitin Rawat authored
Add UFS host controller and PHY nodes for sc7280 IDP board. Signed-off-by:
Nitin Rawat <quic_nitirawa@quicinc.com> Acked-by:
Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by:
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Nitin Rawat authored
Add UFS host controller and PHY nodes for sc7280 soc. Signed-off-by:
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Neil Armstrong authored
Declare the displayport controller present on the Qualcomm SM8650 SoC and connected to the USB3/DP Combo PHY. Signed-off-by:
Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20231208-topic-sm8650-upstream-dp-v2-1-69dab3d074e4@linaro.org Signed-off-by:
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Krzysztof Kozlowski authored
The address/size cells in PWM node are needed only if individual LEDs are listed. If multi-led is used, then this leads to dtc W=1 warnings: pm8550.dtsi:65.19-73.5: Warning (avoid_unnecessary_addr_size): /soc@0/spmi@c400000/pmic@1/pwm: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property Signed-off-by:Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20231208124332.48636-1-krzysztof.kozlowski@linaro.org Signed-off-by:
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- Dec 08, 2023
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Abel Vesa authored
Add basic support for X1E80100 CRD board dts, which allows it to boot to a shell. Signed-off-by:
Abel Vesa <abel.vesa@linaro.org> Signed-off-by:
Rajendra Nayak <quic_rjendra@quicinc.com> Co-developed-by:
Sibi Sankar <quic_sibis@quicinc.com> Signed-off-by:
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Rajendra Nayak authored
Add base dtsi and QCP board (Qualcomm Compute Platform) dts file for X1E80100 SoC, describing the CPUs, GCC and RPMHCC clock controllers, geni UART, interrupt controller, TLMM, reserved memory, interconnects, SMMU and LLCC nodes. Co-developed-by:
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Rajendra Nayak authored
Document the X1E80100 SoC binding and also the boards using it. Also document the new board id qcp (Qualcomm Compute Platform). Signed-off-by:
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Rajendra Nayak authored
Oryon is the custom ARM CPU core implementation used in Qualcomm's X1E80100 SoC, document it. Signed-off-by:
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Bjorn Andersson authored
Merge branch 'icc-x1e80100' of https://git.kernel.org/pub/scm/linux/kernel/git/djakov/icc into arm64-for-6.8 Merge the X1E80100 interconnect binding to get access to the interconnect port constants.
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Bjorn Andersson authored
Merge the X1E80100 clock bindings to get access to the clock constants.
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Rajendra Nayak authored
Add bindings and update documentation for clock rpmh driver on X1E80100 SoCs. Signed-off-by:
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Rajendra Nayak authored
Add device tree bindings for global clock controller on X1E80100 SoCs. Signed-off-by:
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Krzysztof Kozlowski authored
Add nodes for WSA8845 speakers on SM8650 MTP board. Cc: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by:
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Krzysztof Kozlowski authored
Add nodes for LPASS Soundwire v2.0.0 controllers. Use labels with indices matching downstream DTS, to make any comparisons easier. Cc: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by:
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Krzysztof Kozlowski authored
Add the Low Power Audio SubSystem (LPASS) / ADSP audio codec macros on Qualcomm SM8650. The nodes are very similar to SM8550. Cc: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by:
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Krzysztof Kozlowski authored
Add the Low Power Audio SubSystem Low Power Island (LPASS LPI) pin controller device node as part of audio subsystem in Qualcomm SM8650 SoC. Cc: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by:
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Krzysztof Kozlowski authored
Add the ADSP Generic Packet Router (GPR) device node as part of audio subsystem in Qualcomm SM8650 SoC. Cc: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by:
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Neil Armstrong authored
Enable IPA on the SM8650 QRD. The GSI firmware on this platform is loaded by the AP. Signed-off-by:
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Neil Armstrong authored
Add IPA-related nodes and definitions to SM8650 dtsi, which uses IPA v5.5.1 a minor revision of v5.5 found in the SM8550 SoC. Signed-off-by:
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Neil Armstrong authored
Now interconnect dependent devices are added in sm8650 DTSI, now enable more devices for the Qualcomm SM8650 QRD board: - PCIe - Display - DSPs - SDCard - UFS - USB role switch with PMIC Glink - Bluetooth Reviewed-by:
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Neil Armstrong authored
Now interconnect dependent devices are added in sm8650 DTSI, now enable more devices for the Qualcomm SM8650 MTP board: - PCIe - Display - DSPs - SDCard - UFS - USB role switch with PMIC Glink Reviewed-by:
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Neil Armstrong authored
Add Hardware nodes that depends on an interconnect property to be valid. The includes: - all QUP i2s/spi nodes - PCIe - UFS - SDHCI - Display - HWMON Acked-by:
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Neil Armstrong authored
Add initial QRD (Qualcomm Reference Device) DT, it supports boot to shell with buttons, leds and USB peripheral. Reviewed-by:
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Neil Armstrong authored
Add initial QRD (Qualcomm Reference Device) DT, only boots to shell with USB device support. Reviewed-by:
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Neil Armstrong authored
The pm8550ve can be found with a different SID on SM8650 platforms, make it configurable. Reviewed-by:
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Neil Armstrong authored
Add initial DTSI for the Qualcomm SM8650 platform, only contains nodes which doesn't depend on interconnect. Reviewed-by:
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Neil Armstrong authored
Document the SM8650 SoC and based MTP (Mobile Test Platforms) and QRD (Qualcomm Reference Device) boards. Reviewed-by:
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