- Aug 02, 2023
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Dmitry Baryshkov authored
The feature bits DPU_MDP_BWC, DPU_MDP_UBWC_1_0, and DPU_MDP_UBWC_1_5 are not used by the driver, drop them completely. Signed-off-by:
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by:
Abhinav Kumar <quic_abhinavk@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/550056/ Link: https://lore.kernel.org/r/20230728213320.97309-8-dmitry.baryshkov@linaro.org Signed-off-by:
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Dmitry Baryshkov authored
As the DPU driver has switched to fetching data from MDSS driver, we can now drop the UBWC and highest_bank_bit parts of the DPU hw catalog. Reviewed-by:
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Dmitry Baryshkov authored
Switch to using data from MDSS driver to program the SSPP fetch and UBWC configuration. As a side-effect, this also swithes the DPU driver from DPU_HW_UBWC_VER_xx values to the UBWC_x_y enum, which reflects the hardware register values. Signed-off-by:
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Dmitry Baryshkov authored
As we are going to use MDSS data for DPU programming, populate missing MDSS data. The UBWC 1.0 and no UBWC cases do not require MDSS programming, so skip them. Signed-off-by:
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Dmitry Baryshkov authored
DPU programming requires knowledge of some of UBWC parameters. This results in duplication of UBWC data between MDSS and DPU drivers. Export the required data from MDSS driver. Reviewed-by:
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Dmitry Baryshkov authored
Rename the ubwc_version field to ubwc_enc_version, it denotes the version of the UBWC encoder, not the "UBWC version". Reviewed-by:
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Dmitry Baryshkov authored
The SM8550 platform employs newer UBWC decoder, which requires slightly different programming. Fixes: a2f33995 ("drm/msm: mdss: add support for SM8550") Signed-off-by:
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Dmitry Baryshkov authored
While reworking interrupts masks, it was easier to keep old MDP_INTFn_7xxx_INTR and MDP_INTFn_7xxx_TEAR_INTR symbols. Now it is time to drop them and use unified symbol names. Reviewed-by:
Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by:
Marijn Suijten <marijn.suijten@somainline.org> Signed-off-by:
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Dmitry Baryshkov authored
Now as the list of the interrupts is constructed from the catalog data, drop the mdss_irqs field from catalog. Reviewed-by:
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Dmitry Baryshkov authored
Declaring the mask of supported interrupts proved to be error-prone. It is very easy to add a bit with no corresponding backing block or to miss the INTF TE bit. Replace this with looping over the enabled INTF blocks to setup the irq mask. Reviewed-by:
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Dmitry Baryshkov authored
There is no point in having a single enum (and a single array) for both DPU < 7.0 and DPU >= 7.0 interrupt registers. Instead define a single enum and two IRQ address arrays. Reviewed-by:
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Dmitry Baryshkov authored
Inline __intr_offset(), there is no point in having a separate oneline function for setting base block address. Reviewed-by:
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Ruan Jinjie authored
There is no need to call the DRM_DEV_ERROR() function directly to print a custom message when handling an error from platform_get_irq() function as it is going to display an appropriate error message in case of a failure. Signed-off-by:
Ruan Jinjie <ruanjinjie@huawei.com> Reviewed-by:
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Amit Pundir authored
Add and document the reserved memory region property in the mdss-common schema. For now (sdm845-db845c), it points to a framebuffer memory region reserved by the bootloader for splash screen. Acked-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by:
Rob Herring <robh@kernel.org> Signed-off-by:
Amit Pundir <amit.pundir@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/549376/ Link: https://lore.kernel.org/r/20230726132719.2117369-1-amit.pundir@linaro.org Signed-off-by:
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- Jul 27, 2023
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Marijn Suijten authored
SM6125 features only a single PHY (despite a secondary PHY PLL source being available to the disp_cc_mdss_pclk0_clk_src clock), and downstream sources for this "trinket" SoC do not define the typical "vcca" regulator to be available nor used. This, including the register offset is identical to QCM2290, whose config struct can trivially be reused. Reviewed-by:
Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by:
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Marijn Suijten authored
Document availability of the 14nm DSI PHY on SM6125. Note that this compatible uses the SoC-suffix variant, intead of postfixing an arbitrary number without the sm/sdm portion. The PHY is not powered by a vcca regulator like on most SoCs, but by the MX power domain that is provided via the power-domains property and a single corresponding required-opps. Acked-by:
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Marijn Suijten authored
SM6125 has an UBWC 3.0 decoder but only an UBWC 1.0 encoder. Reviewed-by:
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Marijn Suijten authored
Add definitions for the display hardware used on the Qualcomm SM6125 platform. Reviewed-by:
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Marijn Suijten authored
Document the SM6125 MDSS. Reviewed-by:
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Marijn Suijten authored
SM6125 is identical to SM6375 including the throttle clock that is also provided to the MDP node downstream. Note that any SoC other than SM6375 (currently SC7180 and SM6350) has an unconstrained maximum number of clocks and could either pass or leave out this "throttle" clock. Signed-off-by:
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Marijn Suijten authored
Document general compatibility of the DSI controller on SM6125. Reviewed-by:
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Marijn Suijten authored
On SM6125 the dispcc block is gated behind VDDCX: allow this domain to be configured. Acked-by:
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Marijn Suijten authored
The "gcc_disp_gpll0_div_clk_src" clock is consumed by the driver, will be passed from DT, and should be required by the bindings. Fixes: 8397c9c0 ("dt-bindings: clock: add QCOM SM6125 display clock bindings") Reviewed-by:
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Marijn Suijten authored
Both SM6350 and SM6375 support only a single DSI link, and don't have a corresponding dsi1 node in DTS. Their examples should not suggest an output interface port on the display-controller node to this inexistant DSI host, with a dsi1_in label reference that doesn't exist in the example either. Fixes: 3b7502b0 ("dt-bindings: display/msm: Add SM6350 MDSS") Fixes: 2a5c1021 ("dt-bindings: display/msm: Add SM6375 MDSS") Signed-off-by:
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Marijn Suijten authored
The regulator setup was likely copied from other SoCs by mistake. Just like SM6125 the DSI PHY on this platform is not getting power from a regulator but from the MX power domain. Fixes: 572e9fd6 ("drm/msm/dsi: Add phy configuration for QCM2290") Reviewed-by:
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Abhinav Kumar authored
Now that all usages of DPU_INTF_DATA_COMPRESS have been replaced with the dpu core's major revision lets drop DPU_INTF_DATA_COMPRESS from the catalog completely. Signed-off-by:
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Abhinav Kumar authored
Rename the intf's enable_compression() op to program_intf_cmd_cfg() and allow it to accept a struct intf_cmd_mode_cfg to program all the bits at once. This can be re-used by widebus later on as well as it touches the same register. changes in v5: - rename struct intf_cmd_mode_cfg to dpu_hw_intf_cmd_mode_cfg - remove couple of comments Signed-off-by:
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Abhinav Kumar authored
dpu_hw_intf has a few instances of structs which do not have the dpu_hw prefix. Lets fix this by renaming those structs and updating the usage of those accordingly. Signed-off-by:
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Abhinav Kumar authored
Instead of using a feature bit to decide whether to enable data compress or not for DSC use-cases, use dpu core's major version instead by assigning the enable_compression op based on the dpu core's major version. To make this possible pass the struct dpu_mdss_version to dpu_hw_intf_init(). This will avoid defining feature bits for every bit level details of registers. changes in v5: - none Reviewed-by:
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Abhinav Kumar authored
Introduce the dpu core revision back as an entry to the catalog so that we can just use dpu revision checks and enable those bits which should be enabled unconditionally and not controlled by a catalog and also simplify the changes to do something like: if (dpu_core_revision > xxxxx && dpu_core_revision < xxxxx) enable the bit; changes in v5: - fix the commit text to remove instances of DPU_HW_VER Reviewed-by:
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Jessica Zhang authored
During a frame transfer in command mode, there could be frequent LP11 <-> HS transitions when multiple DCS commands are sent mid-frame or if the DSI controller is running on slow clock and is throttled. To minimize frame latency due to these transitions, it is recommended to send the frame in a single burst. This feature is supported for DSI 6G 1.3 and above, thus enable burst mode if supported. Signed-off-by:
Jessica Zhang <quic_jesszhan@quicinc.com> Reviewed-by:
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Dmitry Baryshkov authored
It looks like DP controlled on SM8250 is the same as DP controller on SM8350. Use the SM8350 compatible as fallback for SM8250. Signed-off-by:
Bjorn Andersson <andersson@kernel.org> Reviewed-by:
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Ryan McCann authored
Currently, the device core dump mechanism does not dump registers of sub-blocks within the DSPP, SSPP, DSC, and PINGPONG blocks. Edit dpu_kms_mdp_snapshot function to account for sub-blocks. Signed-off-by:
Ryan McCann <quic_rmccann@quicinc.com> Reviewed-by:
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Ryan McCann authored
Currently, the names of main blocks are hardcoded into the msm_disp_snapshot_add_block function rather than using the name that already exists in the catalog. Change this to take the name directly from the catalog instead of hardcoding it. Signed-off-by:
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Ryan McCann authored
For a device core dump, the registers of sub-blocks are printed under a title formatted as <mainBlkName_sblkName>. For example, the csc sub-block for an SSPP main block "sspp_0" would be printed "sspp_0_sspp_csc0". The title is clearly redundant due to the duplicate "sspp" and "0" that exist in both the mainBlkName and sblkName. To eliminate this redundancy, remove the secondary "sspp" and "0" that exist in the sub-block name by elimanting the "sspp_" prefix and the concatenation of "num" that results in the redundant "0" suffix. Remove num parameter altogether from relevant macros as a consequence of it no longer being used. Reviewed-by:
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Ryan McCann authored
Some sub-blocks in the hw catalog have not been given a name, so when the registers from that block are dumped, there is no name to reference. Define names for relevant sub-blocks to fix this. Reviewed-by:
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Ryan McCann authored
Drop unused parameter "num" from VIG_SBLK_NOSCALE and DMA sub-block macros. Update calls to relevant macros to reflect change. Reviewed-by:
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Ryan McCann authored
Device core dump add block method adds hardware blocks to dumping queue with stack behavior which causes the hardware blocks to be printed in reverse order. Change the addition to dumping queue data structure from "list_add" to "list_add_tail" for FIFO queue behavior. Fixes: 98659487 ("drm/msm: add support to take dpu snapshot") Reviewed-by:
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- Jul 12, 2023
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Dmitry Baryshkov authored
The INTF_SDM845_MASK features mask is zero. Drop it completely. Reviewed-by:
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Dmitry Baryshkov authored
The MERGE_3D_SM8150_MASK features mask is zero. Drop it completely. Reviewed-by:
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