- Dec 20, 2023
-
-
Krzysztof Kozlowski authored
Drop common properties already defined in referenced common Qualcomm SoC TLMM bindings and use "unevaluatedProperties: false". This makes the binding smaller and easier to review. In few places move the "required:" block to bottom, to match convention. Signed-off-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20231208215534.195854-9-krzysztof.kozlowski@linaro.org Signed-off-by:
Linus Walleij <linus.walleij@linaro.org>
-
Krzysztof Kozlowski authored
Reference common Qualcomm SoC TLMM bindings to drop commonly used properties and also bring other schemas for common definitions. Signed-off-by:
Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20231208215534.195854-8-krzysztof.kozlowski@linaro.org Signed-off-by:
-
Krzysztof Kozlowski authored
X1E80100 TLMM pin controller comes with only one interrupt, so narrow the number of interrupts previously defined in common TLMM bindings. Signed-off-by:
-
Krzysztof Kozlowski authored
SM8650 TLMM pin controller comes with only one interrupt, so narrow the number of interrupts previously defined in common TLMM bindings. Signed-off-by:
-
Krzysztof Kozlowski authored
SM8550 TLMM pin controller comes with only one interrupt, so narrow the number of interrupts previously defined in common TLMM bindings. Signed-off-by:
-
Krzysztof Kozlowski authored
SDX75 TLMM pin controller comes with only one interrupt, so narrow the number of interrupts previously defined in common TLMM bindings. Signed-off-by:
-
Krzysztof Kozlowski authored
SA8775p TLMM pin controller comes with only one interrupt, so narrow the number of interrupts previously defined in common TLMM bindings. Signed-off-by:
-
Krzysztof Kozlowski authored
QDU1000 TLMM pin controller comes with only one interrupt, so narrow the number of interrupts previously defined in common TLMM bindings. Signed-off-by:
-
Krzysztof Kozlowski authored
Just like regular TLMM pin controllers in Qualcomm SoCs, the Low Power Audio SubSystem (LPASS) Low Power Island (LPI) TLMM blocks share a lot of properties, so common part can be moved to separate schema to reduce code duplication and make reviewing easier. Except the move of common part, this introduces effective changes: 1. To all LPASS LPI bindings: Reference pinmux-node.yaml in each pin muxing and configuration node, to bring definition of "function" and "pins" properties. 2. qcom,sc7280-lpass-lpi-pinctrl: Reference pinctrl.yaml in top leve. Signed-off-by:
-
Tengfei Fan authored
Add pinctrl driver for TLMM block found in SM4450 SoC. Can Guo helped out in reviewing the driver. Reviewed-by:
Bjorn Andersson <andersson@kernel.org> Signed-off-by:
Tengfei Fan <quic_tengfan@quicinc.com> Link: https://lore.kernel.org/r/20231212094900.12615-3-quic_tengfan@quicinc.com Signed-off-by:
-
Tengfei Fan authored
Add device tree binding Documentation details for Qualcomm SM4450 TLMM device. Reviewed-by:
-
Johan Hovold authored
The Multi-Purpose Pin controller block is part of an SPMI PMIC (which in turns sits on an SPMI bus) and uses a single value for the register property that corresponds to its base address. Clean up the example by adding a parent PMIC node with proper '#address-cells' and '#size-cells' properties, dropping the incorrect second register value, adding some newline separators and increasing the indentation to four spaces. Signed-off-by:
Johan Hovold <johan+linaro@kernel.org> Reviewed-by:
-
- Dec 19, 2023
-
-
Linus Walleij authored
Merge tag 'intel-pinctrl-v6.8-1' of git://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/intel into devel intel-pinctrl for v6.8-1 * New agnostic driver to support Lunar Lake and newer platforms * New driver for Intel Meteor Point-S (PCH for Meteor Lake-S) * Update drivers to use new PM helpers * Use RAII for locking in a few drivers (Raag, Andy) * Reduce locking scope in some functions (Raag) * Miscellaneous cleanups (Raag) The following is an automated git shortlog grouped by driver: alderlake: - Switch to use Intel pin control PM ops baytrail: - Simplify code with cleanup helpers - Move default strength assignment to a switch-case - Factor out byt_gpio_force_input_mode() - Fix types of config value in byt_pin_config_set() broxton: - Switch to use Intel pin control PM ops cannonlake: - Switch to use Intel pin control PM ops cedarfork: - Switch to use Intel pin control PM ops denverton: - Switch to use Intel pin control PM ops elkhartlake: - Switch to use Intel pin control PM ops emmitsburg: - Switch to use Intel pin control PM ops geminilake: - Switch to use Intel pin control PM ops icelake: - Switch to use Intel pin control PM ops intel: - Add Intel Meteor Point pin controller and GPIO support - use the correct _PM_OPS() export macro - Add a generic Intel pin control platform driver - Revert "Unexport intel_pinctrl_probe()" - allow independent COMPILE_TEST - Refactor intel_pinctrl_get_soc_data() - Move default strength assignment to a switch-case - Make PM ops functions static - Provide Intel pin control wide PM ops structure jasperlake: - Switch to use Intel pin control PM ops lakefield: - Switch to use Intel pin control PM ops lewisburg: - Switch to use Intel pin control PM ops lynxpoint: - Simplify code with cleanup helpers meteorlake: - Switch to use Intel pin control PM ops sunrisepoint: - Switch to use Intel pin control PM ops tangier: - simplify locking using cleanup helpers - Move default strength assignment to a switch-case - Enable 910 Ohm bias tigerlake: - Switch to use Intel pin control PM ops Signed-off-by:
-
- Dec 18, 2023
-
-
Linus Walleij authored
Merge tag 'samsung-pinctrl-6.8' of https://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/samsung into devel Samsung pinctrl drivers changes for v6.8 1. New hardware: Add pin controllers for Samsung ExynosAutov920 and Google Tensor GS101. 2. Few DT bindings cleanups: add specific compatibles for each device using generic compatible as fallback. This affects only DTS, no driver changes are needed. 3. Allow setting affinity on non wake-up external GPIO interrupts. Signed-off-by:
-
Linus Walleij authored
Merge tag 'renesas-pinctrl-for-v6.8-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: renesas: Updates for v6.8 (take two) - Add pinmux groups, power source, and input/output enable support for Ethernet pins on RZ/G2L SoCs, - Miscellaneous fixes and improvements. Signed-off-by:
-
- Dec 15, 2023
-
-
Andy Shevchenko authored
This driver supports pinctrl/GPIO hardware found on Intel Meteor Point (a Meteor Lake PCH) providing users a pinctrl and GPIO interfaces including GPIO interrupts. Acked-by:
Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by:
Andy Shevchenko <andriy.shevchenko@linux.intel.com>
-
Claudiu Beznea authored
Some of the RZ/G3S Ethernet pins (P1_0, P7_0) can be configured with input enable. Enable this functionality for these pins. Signed-off-by:
Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Reviewed-by:
Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20231207070700.4156557-8-claudiu.beznea.uj@bp.renesas.com Signed-off-by:
-
Claudiu Beznea authored
Some of the Ethernet pins on RZ/G3S (but also valid for RZ/G2L) need to have the direction of the IO buffer set as output for Ethernet to work properly. On RZ/G3S, these pins are P1_0/P7_0, P1_1/P7_1, and can have the following Ethernet functions: TXC/TX_CLK or TX_CTL/TX_EN. As the pins supporting output enable are SoC specific, and there is a limited number of these pins (TXC/TX_CLK and/or TX_CTL/TX_EN), specify output enable capable port limits in the platform-based configuration data structure, to ensure proper validation. The OEN support has been intantiated for RZ/G3S at the moment. Signed-off-by:
-
Claudiu Beznea authored
The GPIO controller available on RZ/G3S (but also on RZ/G2L) supports setting the power source for Ethernet pins. Based on the interface b/w the Ethernet controller and the Ethernet PHY, and on board design, a specific power source needs to be selected. The GPIO controller supports 1.8V, 2.5V, and 3.3V power source selection for the Ethernet pins. This can be selected though the ETHx_POC registers (x={0, 1}). Adjust the driver to support this, and to do proper instantiation for the RZ/G3S and RZ/G2L SoCs. On RZ/G2L only the get operation has been tested at the moment. While at it, as the power registers on RZ/G2L support access sizes of 8 bits, and these registers on RZ/G3S support access sizes of 8/16/32 bits, replace writel()/readl() on these registers with writeb()/readb(). This should allow us to use the same code on both SoCs w/o any issues. Signed-off-by: -
Claudiu Beznea authored
On RZ/G3S different Ethernet pins need to be configured with different settings (e.g. power-source needs to be set, RGMII TXC and TX_CTL pins need output-enable). Adjust the driver to allow specifying pin configuration for pinmux groups. With this, DT settings like the following are taken into account by the driver: eth0_pins: eth0 { tx_ctl { pinmux = <RZG2L_PORT_PINMUX(1, 1, 1)>; /* ET0_TX_CTL */ power-source = <1800>; output-enable; drive-strength-microamp = <5200>; }; }; Signed-off-by:
-
- Dec 14, 2023
-
-
Claudiu Beznea authored
Move arg and index in the main block of the function as they are used by more than one case block of switch-case (3 out of 4 for arg, 2 out of 4 for index). In this way some lines of code are removed. Signed-off-by:
-
- Dec 13, 2023
-
-
Jaewon Kim authored
Add pinctrl data for ExynosAutov920 SoC. It has a newly applied pinctrl register layer for ExynosAuto series. Pinctrl data for ExynosAutoV920 SoC. - GPA0,GPA1 (10): External wake up interrupt - GPQ0 (2): SPMI (PMIC I/F) - GPB0,GPB1,GPB2,GPB3,GPB4,GPB5,GPB6 (47): I2S Audio - GPH0,GPH1,GPH2,GPH3,GPH4,GPH5,GPH6,GPH8 (49): PCIE, UFS, Ethernet - GPG0,GPG1,GPG2,GPG3,GPG4,GPG5 (29): General purpose - GPP0,GPP1,GPP2,GPP3,GPP4,GPP5,GPP6,GPP7,GPP8,GPP9,GPP10 (77): USI Signed-off-by:
Jaewon Kim <jaewon02.kim@samsung.com> Link: https://lore.kernel.org/r/20231211114145.106255-3-jaewon02.kim@samsung.com Signed-off-by:
-
Jaewon Kim authored
New ExynosAuto series GPIO have a different register structure. In the existing Exynos series, EINT control register is enumerated after a specific offset (e.g EXYNOS_GPIO_ECON_OFFSET, EXYNOS_GPIO_EMASK_OFFSET). However, from ExynosAutov920 SoC, the register that controls EINT belongs to each GPIO bank, and each GPIO bank has 0x1000 align. This is a structure to protect the GPIO bank using S2MPU in VM environment, and will only be applied in ExynosAuto series SoCs. -------------------------------------------------------------- | Original Exynos | ExynosAuto | |------------------------------------------------------------| | 0x0 GPIO_CON | 0x0 GPIO_CON | | 0x4 GPIO_DAT | 0x4 GPIO_DAT | | 0x8 GPIO_PUD | 0x8 GPIO_PUD | | 0xc GPIO_DRV | 0xc GPIO_DRV | | 0x10 GPIO_CONPDN | 0x10 GPIO_CONPDN | | 0x14 GPIO_PUDPDN | 0x14 GPIO_PUDPDN | |----------------------------| 0x18 EINT_CON (per_bank) | | ... | 0x1c EINT_FLTCON0 (per_bank) | | ... | 0x20 EINT_FLTCON1 (per_bank) | | ... | 0x24 EINT_MASK (per_bank) | | ... | 0x28 EINT_PEND (per_bank) | |----------------------------|-------------------------------| | 0x700 EINT_CON (global) | ... | | 0x800 EINT_FLTCON (global) | ... | | 0x900 EINT_MASK (global) | ... | | 0xa00 EINT_FEND (global) | ... | -------------------------------------------------------------- Signed-off-by:
-
Linus Walleij authored
Immutable tag for the PEF2256 framer
-
Herve Codina authored
After contributing the driver, add myself as the maintainer for the Lantiq PEF2256 driver. Signed-off-by:
Herve Codina <herve.codina@bootlin.com> Reviewed-by:
Christophe Leroy <christophe.leroy@csgroup.eu> Link: https://lore.kernel.org/r/20231128132534.258459-6-herve.codina@bootlin.com Signed-off-by:
-
Herve Codina authored
The Lantiq PEF2256 is a framer and line interface component designed to fulfill all required interfacing between an analog E1/T1/J1 line and the digital PCM system highway/H.100 bus. This kind of component can be found in old telecommunication system. It was used to digital transmission of many simultaneous telephone calls by time-division multiplexing. Also using HDLC protocol, WAN networks can be reached through the framer. This pinmux support handles the pin muxing part (pins RP(A..D) and pins XP(A..D)) of the PEF2256. Signed-off-by:
-
Herve Codina authored
The Lantiq PEF2256 is a framer and line interface component designed to fulfill all required interfacing between an analog E1/T1/J1 line and the digital PCM system highway/H.100 bus. Signed-off-by:
Jakub Kicinski <kuba@kernel.org> Link: https://lore.kernel.org/r/20231128132534.258459-4-herve.codina@bootlin.com Signed-off-by:
-
Herve Codina authored
The Lantiq PEF2256 is a framer and line interface component designed to fulfill all required interfacing between an analog E1/T1/J1 line and the digital PCM system highway/H.100 bus. Signed-off-by:
-
Herve Codina authored
A framer is a component in charge of an E1/T1 line interface. Connected usually to a TDM bus, it converts TDM frames to/from E1/T1 frames. It also provides information related to the E1/T1 line. The framer framework provides a set of APIs for the framer drivers (framer provider) to create/destroy a framer and APIs for the framer users (framer consumer) to obtain a reference to the framer, and use the framer. This basic implementation provides a framer abstraction for: - power on/off the framer - get the framer status (line state) - be notified on framer status changes - get/set the framer configuration Signed-off-by:
-
Peter Griffin authored
Add support for the pin-controller found on the gs101 SoC used in Pixel 6 phones. Reviewed-by:
Sam Protsenko <semen.protsenko@linaro.org> Signed-off-by:
Peter Griffin <peter.griffin@linaro.org> Acked-by:
-
- Dec 12, 2023
-
-
Andy Shevchenko authored
All drivers are converted to use embedded struct pingroup. Remove unused members from struct group_desc. Reviewed-by:
-
Andy Shevchenko authored
Convert drivers to use grp member embedded in struct group_desc, because other members will be removed to avoid duplication and desynchronisation of the generic pin group description. Reviewed-by:
Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by:
-
Andy Shevchenko authored
Convert drivers to use grp member embedded in struct group_desc, because other members will be removed to avoid duplication and desynchronisation of the generic pin group description. Reviewed-by:
-
Andy Shevchenko authored
Convert drivers to use grp member embedded in struct group_desc, because other members will be removed to avoid duplication and desynchronisation of the generic pin group description. Signed-off-by:
-
Andy Shevchenko authored
Convert drivers to use grp member embedded in struct group_desc, because other members will be removed to avoid duplication and desynchronisation of the generic pin group description. Signed-off-by:
-
Andy Shevchenko authored
Convert drivers to use grp member embedded in struct group_desc, because other members will be removed to avoid duplication and desynchronisation of the generic pin group description. Acked-by:
Paul Cercueil <paul@crapouillou.net> Signed-off-by:
-
Andy Shevchenko authored
Convert drivers to use grp member embedded in struct group_desc, because other members will be removed to avoid duplication and desynchronisation of the generic pin group description. Signed-off-by:
-
Andy Shevchenko authored
Convert drivers to use grp member embedded in struct group_desc, because other members will be removed to avoid duplication and desynchronisation of the generic pin group description. Signed-off-by:
-
Andy Shevchenko authored
Convert drivers to use grp member embedded in struct group_desc, because other members will be removed to avoid duplication and desynchronisation of the generic pin group description. Tested-by:
Florian Fainelli <florian.fainelli@broadcom.com> Reviewed-by:
-
Andy Shevchenko authored
struct group_desc is a particular version of the struct pingroup with associated opaque data. Start switching pin control core and drivers to use it explicitly. Reviewed-by:
-
