- Oct 10, 2023
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Konrad Dybcio authored
When opp-supported-hw is present under an OPP node, but no form of opp_set_supported_hw() has been called, that OPP is ignored by the API and marked as unsupported. Before Commit c928a05e ("drm/msm/adreno: Move speedbin mapping to device table"), an unknown speedbin would result in marking all OPPs as available, but it's better to avoid potentially overclocking the silicon - the GMU will simply refuse to power up the chip. Currently, the Adreno speedbin code does just that (AND returns an invalid error, (int)UINT_MAX). Fix that by defaulting to speedbin 0 (which is conveniently always bound to fuseval == 0). Fixes: c928a05e ("drm/msm/adreno: Move speedbin mapping to device table") Signed-off-by:
Konrad Dybcio <konrad.dybcio@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/559604/ Signed-off-by:
Rob Clark <robdclark@chromium.org>
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Konrad Dybcio authored
SM6375 comes with a patchlevel=1. Fix the chipid up to reflect that. Fixes: 90b593ce ("drm/msm/adreno: Switch to chip-id for identifying GPU") Signed-off-by:
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Konrad Dybcio authored
Some GPUs - particularly A7xx ones - are really really stubborn and sometimes take a longer-than-expected time to finish unhalting GBIF. Note that this is not caused by the request a few lines above. Poll for the unhalt ack to make sure we're not trying to write bits to an essentially dead GPU that can't receive data on its end of the bus. Failing to do this will result in inexplicable GMU timeouts or worse. This is a rather ugly hack which introduces a whole lot of latency. Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-QRD Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> # sm8450 Signed-off-by:
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Konrad Dybcio authored
A740 builds upon the A730 IP, shuffling some values and registers around. More differences will appear when things like BCL are implemented. adreno_is_a740_family is added in preparation for more A7xx GPUs, the logic checks will be valid resulting in smaller diffs. Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-QRD Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> # sm8450 Signed-off-by:
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Konrad Dybcio authored
Add support for Adreno 730, also known as GEN7_0_x, found on SM8450. Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-QRD Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> # sm8450 Signed-off-by:
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Konrad Dybcio authored
Provide the necessary alternations to mostly support state dumping on A7xx. Newer GPUs will probably require more changes here. Crashdumper and debugbus remain untested. Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-QRD Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> # sm8450 Signed-off-by:
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Konrad Dybcio authored
The QMP mailbox expects to be notified of the ACD (Adaptive Clock Distribution) state. Get a handle to the mailbox at probe time and poke it at GMU resume. Since we don't fully support ACD yet, hardcode the message to "val: 0" (state = disabled). Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-QRD Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> # sm8450 Signed-off-by:
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Konrad Dybcio authored
A7xx GPUs are - from kernel's POV anyway - basically another generation of A6xx. They build upon the A650/A660_family advancements, skipping some writes (presumably more values are preset correctly on reset), adding some new ones and changing others. One notable difference is the introduction of a second shadow, called BV. To handle this with the current code, allocate it right after the current RPTR shadow. BV handling and .submit are mostly based on Jonathan Marek's work. All A7xx GPUs are assumed to have a GMU. A702 is not an A7xx-class GPU, it's a weird forked A610. Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-QRD Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> # sm8450 Signed-off-by:
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Konrad Dybcio authored
Add some missing definitions required for A7 support. This may be substituted with a mesa header sync. Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-QRD Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> # sm8450 Signed-off-by:
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Konrad Dybcio authored
Allow A7xx SKUs, such as the A730 GPU found on SM8450 and friends. They use GMU for all things DVFS, just like most A6xx GPUs. Reviewed-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-QRD Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> # sm8450 Signed-off-by:
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Konrad Dybcio authored
When booting the GMU, the QMP mailbox should be pinged about some tunables (e.g. adaptive clock distribution state). To achieve that, a reference to it is necessary. Allow it and require it with A730. Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-QRD Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> # sm8450 Acked-by:
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Konrad Dybcio authored
The GMU on the A7xx series is pretty much the same as on the A6xx parts. It's now "smarter", needs a bit less register writes and controls more things (like inter-frame power collapse) mostly internally (instead of us having to write to G[PM]U_[CG]X registers from APPS) The only difference worth mentioning is the now-required DEMET clock, which is strictly required for things like asserting reset lines, not turning it on results in GMU not being fully functional (all OOB requests would fail and HFI would hang after the first submitted OOB). Describe the A730 and A740 GMU. Reviewed-by:
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- Oct 09, 2023
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Rob Herring authored
Make it explicit that child nodes have additional properties and the child node schema is not complete. The complete schemas are applied separately based the compatible strings. Signed-off-by:
Rob Herring <robh@kernel.org> Acked-by:
Conor Dooley <conor.dooley@microchip.com> Patchwork: https://patchwork.freedesktop.org/patch/559387/ Link: https://lore.kernel.org/r/20230925212434.1972368-2-robh@kernel.org Signed-off-by:
Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
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Rob Herring authored
Just as unevaluatedProperties or additionalProperties are required at the top level of schemas, they should (and will) also be required for child node schemas. That ensures only documented properties are present for any node. Signed-off-by:
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Dmitry Baryshkov authored
Read the downstream port info and set the subconnector type accordingly. Signed-off-by:
Stephen Boyd <swboyd@chromium.org> Patchwork: https://patchwork.freedesktop.org/patch/555531/ Link: https://lore.kernel.org/r/20230903222432.2894093-1-dmitry.baryshkov@linaro.org
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Stephen Boyd authored
Plugging in an Apple dongle without the HDMI cable attached prints out an error message in the kernel logs when nothing is actually wrong. no downstream ports connected This is because the downstream port for the HDMI connector is not connected, so the Apple dongle reports that as a zero sink count device. Cc: Vinod Polimera <quic_vpolimer@quicinc.com> Cc: Kuogee Hsieh <quic_khsieh@quicinc.com> Signed-off-by:
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Stephen Boyd authored
This function is basically a one-liner when you ignore the debug logging. Just inline the function and drop the log to simplify the code. Suggested-by:
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Dmitry Baryshkov authored
As the INTF is fixed at the encoder creation time, we can move the check whether INTF supports tearchck to dpu_encoder_phys_cmd_init(). This function can return an error if INTF doesn't have required feature. Performing this check in dpu_encoder_phys_cmd_tearcheck_config() is less useful, as this function returns void. Signed-off-by:
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Dmitry Baryshkov authored
The dpu_encoder_phys_cmd_te_rd_ptr_irq() function uses neither hw_intf nor hw_pp data, so we can drop the corresponding check. Reviewed-by:
Marijn Suijten <marijn.suijten@somainline.org> Signed-off-by:
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Dmitry Baryshkov authored
Replace the only user of the DPU_INTF_TE feature flag with the direct DPU version comparison. Reviewed-by:
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Dmitry Baryshkov authored
The DPU_INTF_TE bit is set for all INTF blocks on DPU >= 5.0, however only INTF_1 and INTF_2 actually support tearing control (both are INTF_DSI). Rather than trying to limit the DPU_INTF_TE feature bit to those two INTF instances, check for the major && INTF type. Reviewed-by:
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Dmitry Baryshkov authored
Inline the _setup_intf_ops() function, it makes it easier to handle different conditions involving INTF configuration. Reviewed-by:
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Dmitry Baryshkov authored
The DPU_PINGPONG_TE flag became unused, we can drop it now. Reviewed-by:
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Dmitry Baryshkov authored
The DPU_PINGPONG_TE bit is set for all PINGPONG blocks on DPU < 5.0. Rather than checking for the flag, check for the presense of the corresponding interrupt line. Reviewed-by:
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Dmitry Baryshkov authored
Inline the _setup_pingpong_ops() function, it makes it easier to handle different conditions involving PINGPONG configuration. Reviewed-by:
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Jani Nikula authored
The DP CTS test for EDID last block checksum expects the checksum for the last block, invalid or not. Skip the validity check. For the most part (*), the EDIDs returned by drm_get_edid() will be valid anyway, and there's the CTS workaround to get the checksum for completely invalid EDIDs. See commit 7948fe12 ("drm/msm/dp: return correct edid checksum after corrupted edid checksum read"). This lets us remove one user of drm_edid_block_valid() with hopes the function can be removed altogether in the future. (*) drm_get_edid() ignores checksum errors on CTA extensions. Cc: Abhinav Kumar <quic_abhinavk@quicinc.com> Cc: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Cc: Kuogee Hsieh <khsieh@codeaurora.org> Cc: Marijn Suijten <marijn.suijten@somainline.org> Cc: Rob Clark <robdclark@gmail.com> Cc: Sean Paul <sean@poorly.run> Cc: Stephen Boyd <swboyd@chromium.org> Cc: linux-arm-msm@vger.kernel.org Cc: freedreno@lists.freedesktop.org Signed-off-by:
Jani Nikula <jani.nikula@intel.com> Reviewed-by:
Abhinav Kumar <quic_abhinavk@quicinc.com> Reviewed-by:
Kuogee Hsieh <quic_khsieh@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/555361/ Link: https://lore.kernel.org/r/20230901142034.580802-1-jani.nikula@intel.com Signed-off-by:
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Stephen Boyd authored
This function is simply drm_dp_is_branch() so use that instead of open-coding it. Cc: Vinod Polimera <quic_vpolimer@quicinc.com> Cc: Kuogee Hsieh <quic_khsieh@quicinc.com> Signed-off-by:
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Stephen Boyd authored
The function dp_link_parse_sink_count() is really just drm_dp_read_sink_count(). It debug prints out the bit for content protection (DP_SINK_CP_READY), but that is not useful beyond debug because 'link->dp_link.sink_count' is overwritten to only contain the sink_count in this same function. Just use drm_dp_read_sink_count() in the one place this function is called to simplify. Cc: Vinod Polimera <quic_vpolimer@quicinc.com> Cc: Kuogee Hsieh <quic_khsieh@quicinc.com> Signed-off-by:
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Stephen Boyd authored
These are open-coded versions of common functions. Replace them with the common code to improve readability. Cc: Vinod Polimera <quic_vpolimer@quicinc.com> Cc: Kuogee Hsieh <quic_khsieh@quicinc.com> Signed-off-by:
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Stephen Boyd authored
The member 'aux_cfg_update_done' is always false. This is dead code that never runs. Remove it. Cc: Vinod Polimera <quic_vpolimer@quicinc.com> Cc: Kuogee Hsieh <quic_khsieh@quicinc.com> Signed-off-by:
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Stephen Boyd authored
We read the downstream port count and capability info but never use it anywhere. Remove 'ds_port_cnt' and 'ds_cap_info' and any associated code from this driver. Fold the check for 'dfp_present' into a call to drm_dp_is_branch() at the one place it is used to get rid of any member storage related to downstream ports. Cc: Vinod Polimera <quic_vpolimer@quicinc.com> Cc: Kuogee Hsieh <quic_khsieh@quicinc.com> Signed-off-by:
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Stephen Boyd authored
Use the common function drm_dp_read_sink_count() instead of open-coding it. This shrinks the kernel text a tiny bit. Cc: Vinod Polimera <quic_vpolimer@quicinc.com> Cc: Kuogee Hsieh <quic_khsieh@quicinc.com> Signed-off-by:
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Stephen Boyd authored
This function duplicates the common function drm_dp_read_dpcd_caps(). The array of DPCD registers filled in is one size larger than the function takes, but from what I can tell that extra byte was never used. Resize the array and use the common function to reduce the code here. Cc: Vinod Polimera <quic_vpolimer@quicinc.com> Cc: Kuogee Hsieh <quic_khsieh@quicinc.com> Signed-off-by:
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Jessica Zhang authored
DSI 6G v2.5.x+ supports a data-bus widen mode that allows DSI to send 48 bits of compressed data instead of 24. Enable this mode whenever DSC is enabled for supported chipsets. Signed-off-by:
Jessica Zhang <quic_jesszhan@quicinc.com> Reviewed-by:
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Jessica Zhang authored
Add a DATABUS_WIDEN bit to the MDP_CTRL2 register to allow DSI to enable databus widen mode. Reviewed-by:
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Jessica Zhang authored
DPU supports a data-bus widen mode for DSI INTF. Enable this mode for all supported chipsets if widebus is enabled for DSI. Signed-off-by:
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Jessica Zhang authored
Move the setting of dpu_enc::wide_bus_en to dpu_encoder_virt_atomic_enable() so that it mirrors how dpu_enc::dsc is being set. Since wide bus for DSI is related to DSC, having it mirror how DSC is set in DPU will also make it easier to accommodate for the possibility of DSC for DSI being set during runtime in the future. Reviewed-by:
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Ruan Jinjie authored
The NULL initialization of the pointers assigned by kzalloc() first is not necessary, because if the kzalloc() failed, the pointers will be assigned NULL, otherwise it works as usual. so remove it. Signed-off-by:
Ruan Jinjie <ruanjinjie@huawei.com> Reviewed-by:
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Dmitry Baryshkov authored
In order to simplify IRQ declarations, shift IRQ indices by 1. This makes 0 the 'no IRQ' value. Thanks to this change, we do no longer have to explicitly set the 'no interrupt' fields in catalog structures. Reviewed-by:
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Dmitry Baryshkov authored
In preparation to reworking IRQ indcies, stop using raw indices in kernel traces. Instead use a pair of register index and bit. This corresponds closer to the values in HW catalog. Reviewed-by:
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