- Apr 24, 2017
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Andrew Lunn authored
Armada 370/XP devices can 'blink' GPIO lines with a configurable on and off period. This can be modelled as a PWM. However, there are only two sets of PWM configuration registers for all the GPIO lines. This driver simply allows a single GPIO line per GPIO chip of 32 lines to be used as a PWM. Attempts to use more return EBUSY. Due to the interleaving of registers it is not simple to separate the PWM driver from the GPIO driver. Thus the GPIO driver has been extended with a PWM driver. Signed-off-by:
Andrew Lunn <andrew@lunn.ch> URL: https://patchwork.ozlabs.org/patch/427287/ URL: https://patchwork.ozlabs.org/patch/427295/ [Ralph Sennhauser: * Port forward * Merge PWM portion into gpio-mvebu.c * Switch to atomic PWM API * Add new compatible string marvell,armada-370-xp-gpio * Update and merge documentation patch * Update MAINTAINERS] Signed-off-by:
Ralph Sennhauser <ralph.sennhauser@gmail.com> Tested-by:
Thierry Reding <thierry.reding@gmail.com> Acked-by:
Rob Herring <robh@kernel.org> Signed-off-by:
Linus Walleij <linus.walleij@linaro.org>
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- Apr 13, 2017
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Thierry Reding authored
Interrupt numbers are never negative, zero serves as the special invalid value. Signed-off-by:
Thierry Reding <treding@nvidia.com> Signed-off-by:
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- Apr 07, 2017
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Marty Plummer authored
Add F71889A GPIO support. Fintek F71889A is a SuperIO. It contains HWMON/GPIO/Serial Ports. Datasheet: http://www.alldatasheet.com/datasheet-pdf/pdf/459076/FINTEK/F71889A.html Its virtually identical to the F71889F superio as far as gpios go. One oddity is GPIO2 at index 0xD0; the datasheet only lists gpio's 7-5, but it logically seems that it should continue down to 0. I'm not sure if the driver can handle gpios that are shifted away from index 0 as it currently stands. Signed-off-by:
Marty Plummer <netz.kernel@gmail.com> Signed-off-by:
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Laxman Dewangan authored
Currently, the GPIO interface is said to Open Drain if it is Single Ended and active LOW. Similarly, it is said as Open Source if it is Single Ended and active HIGH. The active HIGH/LOW is used in the interface for setting the pin state to HIGH or LOW when enabling/disabling the interface. In Open Drain interface, pin is set to HIGH by putting pin in high impedance and LOW by driving to the LOW. In Open Source interface, pin is set to HIGH by driving pin to HIGH and set to LOW by putting pin in high impedance. With above, the Open Drain/Source is unrelated to the active LOW/HIGH in interface. There is interface where the enable/disable of interface is ether active LOW or HIGH but it is Open Drain type. Hence decouple the Open Drain with Single Ended + Active LOW and Open Source with Single Ended + Active HIGH. Adding different flag for the Open Drain/Open Source which is valid only when Single ended flag is enabled. Signed-off-by:
Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by:
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Charles Keepax authored
The GPIO register is cached since all the configuration resides within it, however, this means for input GPIOs the driver will not return the actual state but the last value written to the register cache. To correct this in the case of reading an input GPIO resume the CODEC and drop the cache for the input register to ensure an actual hardware read takes place. Signed-off-by:
Charles Keepax <ckeepax@opensource.wolfsonmicro.com> Signed-off-by:
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- Mar 28, 2017
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Julia Cartwright authored
The 104-idi-48 gpio driver currently implements an irq_chip for handling interrupts; due to how irq_chip handling is done, it's necessary for the irq_chip methods to be invoked from hardirq context, even on a a real-time kernel. Because the spinlock_t type becomes a "sleeping" spinlock w/ RT kernels, it is not suitable to be used with irq_chips. A quick audit of the operations under the lock reveal that they do only minimal, bounded work, and are therefore safe to do under a raw spinlock. Signed-off-by:
Julia Cartwright <julia@ni.com> Acked-by:
William Breathitt Gray <vilhelm.gray@gmail.com> Signed-off-by:
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Julia Cartwright authored
The pci-idio-16 gpio driver currently implements an irq_chip for handling interrupts; due to how irq_chip handling is done, it's necessary for the irq_chip methods to be invoked from hardirq context, even on a a real-time kernel. Because the spinlock_t type becomes a "sleeping" spinlock w/ RT kernels, it is not suitable to be used with irq_chips. A quick audit of the operations under the lock reveal that they do only minimal, bounded work, and are therefore safe to do under a raw spinlock. Signed-off-by:
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Julia Cartwright authored
The 104-idio-16 gpio driver currently implements an irq_chip for handling interrupts; due to how irq_chip handling is done, it's necessary for the irq_chip methods to be invoked from hardirq context, even on a a real-time kernel. Because the spinlock_t type becomes a "sleeping" spinlock w/ RT kernels, it is not suitable to be used with irq_chips. A quick audit of the operations under the lock reveal that they do only minimal, bounded work, and are therefore safe to do under a raw spinlock. Signed-off-by:
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- Mar 24, 2017
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Russell King authored
Add support for mapping gpio-reg gpios to interrupts. This may be a non-linear mapping - some gpios in the register may not even have corresponding interrupts associated with them, so we need to pass an array. Signed-off-by:
Russell King <rmk+kernel@armlinux.org.uk> Signed-off-by:
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Russell King authored
Add a simple, generic, single register fixed-direction GPIO driver. This is able to support a single register with a mixture of inputs and outputs. This is different from gpio-mmio and gpio-74xx-mmio: * gpio-mmio doesn't allow a fixed direction, it assumes there is always a direction register. * gpio-74xx-mmio only supports all-in or all-out setups * gpio-74xx-mmio is DT only, this needs to support legacy too * they don't double-read when getting the GPIO value, as required by some implementations that this driver supports * we need to always do 32-bit reads, which bgpio doesn't guarantee * the current output state may not be readable from the hardware register - reading may reflect input status but not output status. Signed-off-by:
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Russell King authored
Allow gpiolib to read back the current IO direction configuration by implementing the .get_direction callback. This, in part, allows debugfs to report the complete true hardware state rather than the software state. Signed-off-by:
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Russell King authored
Use IO accessors to access the SA1100 registers rather than accessing them directly. Signed-off-by:
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Russell King authored
Use sa11x0_gpio_set_wake() to set the PWER register, as provided by Dmitry some time back. Signed-off-by:
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- Mar 23, 2017
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Andy Shevchenko authored
The mentioned flags are dedicated solely for consumer API. Replace them by explicit values. Signed-off-by:
Andy Shevchenko <andriy.shevchenko@linux.intel.com> [Made a !bang clamp to (0,1) instead of infix ? operator] Signed-off-by:
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Andy Shevchenko authored
Switch to use managed variant of acpi_dev_add_driver_gpios() to simplify error path and fix potentially wrong assignment if ->probe() fails. While here, add a debug message in case assignment fails to allow user see the cause of a potential issue. Signed-off-by:
Felipe Balbi <felipe.balbi@linux.intel.com> Signed-off-by:
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Andy Shevchenko authored
GPIO ACPI library is going to be stricter about resources, thus, expand comment regarding "reset" GPIO resource in this driver to clarify its usage in ACPI case. Signed-off-by:
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Andy Shevchenko authored
For sake of better maintenance sort the headers by alphabetical order. Signed-off-by:
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Andy Shevchenko authored
Introduce ->get_direction() callback for the driver. Signed-off-by:
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Ralph Sennhauser authored
Use the BIT macro instead of explicitly shifting bits for some added clarity. Signed-off-by:
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Nathan Sullivan authored
The GPIO-based NAND controller on National Instruments 169445 hardware exposes a set of simple lines for the control signals. Signed-off-by:
Nathan Sullivan <nathan.sullivan@ni.com> Signed-off-by:
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- Mar 22, 2017
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Linus Walleij authored
This just deletes the Moxa ART driver and replaces it with the more versatile Faraday FTGPIO010 driver. Make this default on for ARCH_GEMINI and ARCH_MOXART so we do not get Kconfig glitches. Tested-by:
Jonas Jensen <jonas.jensen@gmail.com> Signed-off-by:
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Linus Walleij authored
The Gemini driver is actually a driver for the Faraday Technology FTGPIO010 IP block. We rename the driver and the Kconfig symbol and put in a a new compatible string for the Moxa ART SoC that is also using this IP block. Tested-by:
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Linus Walleij authored
The DT bindings assumed that this IP block was coming from Cortina Systems, which turns out not to be true. It is a standard IP block from Faraday Technology and also used in the Moxa moxart SoC. We augment the bindings to cover all existing parts and rename it after the IP block. This involves deleting the old Moxa bindings that now are contained in this binding. Cc: devicetree@vger.kernel.org Cc: Jonas Jensen <jonas.jensen@gmail.com> Acked-by:
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- Mar 17, 2017
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Ralph Sennhauser authored
A modern compiler should know better when to inline, so drop the inline keywords. Signed-off-by:
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Ralph Sennhauser authored
Fix whitespace errors missed by checkpatch. Signed-off-by:
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Ralph Sennhauser authored
Fix whitespace errors reported by checkpatch. Signed-off-by:
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Ralph Sennhauser authored
Use unsigned int instead of plain unsigned as reported by checkpatch. Signed-off-by:
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Ralph Sennhauser authored
While this isn't an issue according to checkpatch two styles are used. Add a blank line to the block comments missing a blank line at the start so multiline block comments look the same across the file. Signed-off-by:
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Ralph Sennhauser authored
Fix issues in block comments reported by checkpatch. Signed-off-by:
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Hans de Goede authored
When acpi_dev_gpio_irq_get gets called with an index of say 2, it should not care if acpi_get_gpiod for index 0 or 1 returns -EPROBE_DEFER. This allows drivers which request a gpioint with index > 0 to function if there is no gpiochip driver (loaded) for gpioints with a lower index. Signed-off-by:
Hans de Goede <hdegoede@redhat.com> Signed-off-by:
Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by:
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Andy Shevchenko authored
Since gpiod_count() does not return 0 anymore, we don't need to shadow its error code and would safely propagate to the user. While here, replace second parameter by NULL in order to prevent side effects on _DSD enabled firmware. Cc: Benjamin Tissoires <benjamin.tissoires@redhat.com> Signed-off-by:
Dmitry Torokhov <dmitry.torokhov@gmail.com> Signed-off-by:
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Andy Shevchenko authored
Since gpiod_count() does not return 0 anymore, we don't need to shadow its error code and would safely propagate to the user. While here, replace second parameter by NULL in order to prevent side effects on _DSD enabled firmware. Cc: Benjamin Tissoires <benjamin.tissoires@redhat.com> Signed-off-by:
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Andy Shevchenko authored
It's unusual to have error checking like (ret <= 0) in cases when counting GPIO resources. In case when it's mandatory we propagate the error (-ENOENT), otherwise we don't use the result. This makes consistent behaviour across all possible variants called in gpiod_count(). Signed-off-by:
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Andy Shevchenko authored
It's unusual to have error checking like (ret <= 0) in cases when counting GPIO resources. In case when it's mandatory we propagate the error (-ENOENT), otherwise we don't use the result. This makes consistent behaviour across all possible variants called in gpiod_count(). Signed-off-by:
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Jayachandran C authored
ARCH_VULCAN arm64 platform (for Broadcom Vulcan ARM64 processors) has been discontinued. Cavium's ThunderX2 CN99XX (ARCH_THUNDER2) will be the next revision of this platform. Update compile dependencies and ACPI ID to reflect this change. Signed-off-by:
Jayachandran C <jnair@caviumnetworks.com> [Drop depreciation of ARCH_VULCAN] Signed-off-by:
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Julia Cartwright authored
The zx gpio driver currently implements an irq_chip for handling interrupts; due to how irq_chip handling is done, it's necessary for the irq_chip methods to be invoked from hardirq context, even on a a real-time kernel. Because the spinlock_t type becomes a "sleeping" spinlock w/ RT kernels, it is not suitable to be used with irq_chips. A quick audit of the operations under the lock reveal that they do only minimal, bounded work, and are therefore safe to do under a raw spinlock. Signed-off-by:
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Julia Cartwright authored
The ws16c48 gpio driver currently implements an irq_chip for handling interrupts; due to how irq_chip handling is done, it's necessary for the irq_chip methods to be invoked from hardirq context, even on a a real-time kernel. Because the spinlock_t type becomes a "sleeping" spinlock w/ RT kernels, it is not suitable to be used with irq_chips. A quick audit of the operations under the lock reveal that they do only minimal, bounded work, and are therefore safe to do under a raw spinlock. Signed-off-by:
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Julia Cartwright authored
The pl061 gpio driver currently implements an irq_chip for handling interrupts; due to how irq_chip handling is done, it's necessary for the irq_chip methods to be invoked from hardirq context, even on a a real-time kernel. Because the spinlock_t type becomes a "sleeping" spinlock w/ RT kernels, it is not suitable to be used with irq_chips. A quick audit of the operations under the lock reveal that they do only minimal, bounded work, and are therefore safe to do under a raw spinlock. Signed-off-by:
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Julia Cartwright authored
The etraxfs gpio driver currently implements an irq_chip for handling interrupts; due to how irq_chip handling is done, it's necessary for the irq_chip methods to be invoked from hardirq context, even on a a real-time kernel. Because the spinlock_t type becomes a "sleeping" spinlock w/ RT kernels, it is not suitable to be used with irq_chips. A quick audit of the operations under the lock reveal that they do only minimal, bounded work, and are therefore safe to do under a raw spinlock. Signed-off-by:
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Julia Cartwright authored
The ath79 gpio driver currently implements an irq_chip for handling interrupts; due to how irq_chip handling is done, it's necessary for the irq_chip methods to be invoked from hardirq context, even on a a real-time kernel. Because the spinlock_t type becomes a "sleeping" spinlock w/ RT kernels, it is not suitable to be used with irq_chips. A quick audit of the operations under the lock reveal that they do only minimal, bounded work, and are therefore safe to do under a raw spinlock. Signed-off-by:
Aban Bedel <albeu@free.fr> Signed-off-by:
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