1. Jan 17, 2020
  2. Jan 13, 2020
  3. Jan 10, 2020
    • Olivier Moysan's avatar
      ASoC: stm32: dfsdm: fix 16 bits record · 8e55ea19
      Olivier Moysan authored
      In stm32_afsdm_pcm_cb function, the transfer size is provided in bytes.
      However, samples are copied as 16 bits words from iio buffer.
      Divide by two the transfer size, to copy the right number of samples.
      
      Fixes: 1e7f6e1c
      
       ("ASoC: stm32: dfsdm: add 16 bits audio record support")
      
      Signed-off-by: default avatarOlivier Moysan <olivier.moysan@st.com>
      Link: https://lore.kernel.org/r/20200110131131.3191-1-olivier.moysan@st.com
      
      
      Signed-off-by: default avatarMark Brown <broonie@kernel.org>
      8e55ea19
    • Olivier Moysan's avatar
      ASoC: stm32: sai: fix possible circular locking · a14bf98c
      Olivier Moysan authored
      In current driver, locks can be taken as follows:
      - Register access: take a lock on regmap config and then on clock.
      - Master clock provider: take a lock on clock and then on regmap config.
      This can lead to the circular locking summarized below.
      
      Remove peripheral clock management through regmap framework, and manage
      peripheral clock in driver instead. On register access, lock on clock
      is taken first, which allows to avoid possible locking issue.
      
      [ 6696.561513] ======================================================
      [ 6696.567670] WARNING: possible circular locking dependency detected
      [ 6696.573842] 4.19.49 #866 Not tainted
      [ 6696.577397] ------------------------------------------------------
      [ 6696.583566] pulseaudio/6439 is trying to acquire lock:
      [ 6696.588697] 87b0a25b (enable_lock){..-.}, at: clk_enable_lock+0x64/0x128
      [ 6696.595377]
      [ 6696.595377] but task is already holding lock:
      [ 6696.601197] d858f825 (stm32_sai_sub:1342:(sai->regmap_config)->lock){....}
      ...
      [ 6696.812513]  Possible unsafe locking scenario:
      [ 6696.812513]
      [ 6696.818418]        CPU0                    CPU1
      [ 6696.822935]        ----                    ----
      [ 6696.827451]   lock(stm32_sai_sub:1342:(sai->regmap_config)->lock);
      [ 6696.833618]                                lock(enable_lock);
      [ 6696.839350]                                lock(stm32_sai_sub:1342:
                                                    (sai->regmap_config)->lock);
      [ 6696.848035]   lock(enable_lock);
      
      Fixes: 03e78a24
      
       ("ASoC: stm32: sai: add h7 support")
      
      Signed-off-by: default avatarOlivier Moysan <olivier.moysan@st.com>
      Link: https://lore.kernel.org/r/20200109083254.478-1-olivier.moysan@st.com
      
      
      Signed-off-by: default avatarMark Brown <broonie@kernel.org>
      a14bf98c
  4. Jan 08, 2020
  5. Jan 07, 2020
  6. Jan 03, 2020
  7. Dec 25, 2019
  8. Dec 19, 2019
  9. Dec 16, 2019
  10. Dec 10, 2019
  11. Dec 09, 2019
  12. Dec 04, 2019
  13. Dec 03, 2019
  14. Nov 27, 2019
    • Tzung-Bi Shih's avatar
      ASoC: max98090: fix possible race conditions · 45dfbf56
      Tzung-Bi Shih authored
      
      
      max98090_interrupt() and max98090_pll_work() run in 2 different threads.
      There are 2 possible races:
      
      Note: M98090_REG_DEVICE_STATUS = 0x01.
      Note: ULK == 0, PLL is locked; ULK == 1, PLL is unlocked.
      
      max98090_interrupt      max98090_pll_work
      ----------------------------------------------
      schedule max98090_pll_work
                              restart max98090 codec
      receive ULK INT
                              assert ULK == 0
      schedule max98090_pll_work (1).
      
      In the case (1), the PLL is locked but max98090_interrupt unnecessarily
      schedules another max98090_pll_work.
      
      max98090_interrupt      max98090_pll_work      max98090 codec
      ----------------------------------------------------------------------
                                                     ULK = 1
      receive ULK INT
      read 0x01
                                                     ULK = 0 (clear on read)
      schedule max98090_pll_work
                              restart max98090 codec
                                                     ULK = 1
      receive ULK INT
      read 0x01
                                                     ULK = 0 (clear on read)
                              read 0x01
                              assert ULK == 0 (2).
      
      In the case (2), both max98090_interrupt and max98090_pll_work read
      the same clear-on-read register.  max98090_pll_work would falsely
      thought PLL is locked.
      Note: the case (2) race is introduced by the previous commit ("ASoC:
      max98090: exit workaround earlier if PLL is locked") to check the status
      and exit the loop earlier in max98090_pll_work.
      
      There are 2 possible solution options:
      A. turn off ULK interrupt before scheduling max98090_pll_work; and turn
      on again before exiting max98090_pll_work.
      B. remove the second thread of execution.
      
      Option A cannot fix the case (2) race because it still has 2 threads
      access the same clear-on-read register simultaneously.  Although we
      could suppose the register is volatile and read the status via I2C could
      be much slower than the hardware raises the bits.
      
      Option B introduces a maximum 10~12 msec penalty delay in the interrupt
      handler.  However, it could only punish the jack detection by extra
      10~12 msec.
      
      Adopts option B which is the better solution overall.
      
      Signed-off-by: default avatarTzung-Bi Shih <tzungbi@google.com>
      Link: https://lore.kernel.org/r/20191122073114.219945-4-tzungbi@google.com
      
      
      Reviewed-by: default avatarPierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
      Signed-off-by: default avatarMark Brown <broonie@kernel.org>
      45dfbf56
    • Tzung-Bi Shih's avatar
      ASoC: max98090: exit workaround earlier if PLL is locked · 6f49919d
      Tzung-Bi Shih authored
      
      
      According to the datasheet, PLL lock time typically takes 2 msec and
      at most takes 7 msec.
      
      Check the lock status every 1 msec and exit the workaround if PLL is
      locked.
      
      Signed-off-by: default avatarTzung-Bi Shih <tzungbi@google.com>
      Link: https://lore.kernel.org/r/20191122073114.219945-3-tzungbi@google.com
      
      
      Reviewed-by: default avatarPierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
      Signed-off-by: default avatarMark Brown <broonie@kernel.org>
      6f49919d