- Apr 08, 2021
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Rob Clark authored
So we don't have to duplicate the boilerplate for eviction. This also lets us re-use the main scan loop for vmap shrinker. Signed-off-by:
Rob Clark <robdclark@chromium.org> Link: https://lore.kernel.org/r/20210405174532.1441497-3-robdclark@gmail.com Signed-off-by:
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Rob Clark authored
If you mess something up, you don't really need to see the same warn on splat 4000 times pumped out a slow debug UART port.. Signed-off-by:
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Dmitry Baryshkov authored
Currently DPU driver scales bandwidth and core clock for sc7180 only, while the rest of chips get static bandwidth votes. Make all chipsets scale bandwidth and clock per composition requirements like sc7180 does. Drop old voting path completely. Tested on RB3 (SDM845) and RB5 (SM8250). Signed-off-by:
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20210401020533.3956787-2-dmitry.baryshkov@linaro.org Signed-off-by:
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Dmitry Baryshkov authored
Fill clk_inefficiency_factor, bw_inefficiency_factor and min_prefill_lines in hw catalog data for sdm845 and sm8[12]50. Efficiency factors are blindly copied from sc7180 data, while min_prefill_lines is based on downstream display driver. Signed-off-by:
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Dmitry Baryshkov authored
SM8250 platform has a 8-Levels VIG QoS setting. This setting was missed due to bad interaction with b8dab65b ("drm/msm/dpu: Move DPU_SSPP_QOS_8LVL bit to SDM845 and SC7180 masks"), which was applied in parallel. Fixes: d21fc5df ("drm/msm/dpu1: add support for qseed3lite used on sm8250") Signed-off-by:
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Dmitry Baryshkov authored
Phy driver already knows the source PLL id basing on the set usecase and the current PLL id. Stop passing it to the phy_enable call. As a reminder, dsi manager will always use DSI 0 as a clock master in a slave mode, so PLL 0 is always a clocksource for DSI 0 and it is always a clocksource for DSI 1 too unless DSI 1 is used in the standalone mode. Signed-off-by:
Abhinav Kumar <abhinavk@codeaurora.org> Link: https://lore.kernel.org/r/20210331105735.3690009-25-dmitry.baryshkov@linaro.org Signed-off-by:
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Dmitry Baryshkov authored
The src_truthtable config is not used for some of phys, which use other means of configuring the master/slave usecases. Inline this function with the goal of removing src_pll_id argument in the next commit. Signed-off-by:
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Dmitry Baryshkov authored
The 7nm, 10nm and 14nm drivers would store interim data used during VCO/PLL rate setting in the global dsi_pll_Nnm structure. Move this data structures to the onstack storage. While we are at it, drop unused/static 'config' data, unused config fields, etc. Signed-off-by:
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Dmitry Baryshkov authored
Drop duplicate fields pdev and id from dsi_pll_Nnm instances. Reuse those fields from the provided msm_dsi_phy. Signed-off-by:
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Dmitry Baryshkov authored
All PHY drivers would map dsi_pll area. Some PHY drivers would also map dsi_phy area again (a leftover from old PHY/PLL separation). Move all ioremaps to the common dsi_phy driver code and drop individual ioremapped areas from PHY drivers. Signed-off-by:
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Dmitry Baryshkov authored
Replace PLL accessor functions (pll_read/pll_write*) with the DSI PHY accessors, reducing duplication. Signed-off-by:
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Dmitry Baryshkov authored
Drop the struct msm_dsi_pll abstraction, by including vco's clk_hw directly into struct msm_dsi_phy. Signed-off-by:
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Dmitry Baryshkov authored
Make save_state/restore callbacks accept struct msm_dsi_phy rather than struct msm_dsi_pll. This moves them to struct msm_dsi_phy_ops, allowing us to drop struct msm_dsi_pll_ops. Signed-off-by:
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Dmitry Baryshkov authored
10nm and 7nm already do not use these helpers, as they handle setting slave DSI clocks after enabling VCO. Modify the rest of PHY drivers to remove unnecessary indirection and drop enable_seq/disable_seq PLL callbacks. Signed-off-by:
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Dmitry Baryshkov authored
Instead of setting the variable and then using it just in the one place, determine vco_delay directly at the PLL configuration time. Signed-off-by:
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Dmitry Baryshkov authored
These drivers do not use vco_delay variable, so drop it from all of them. Signed-off-by:
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Dmitry Baryshkov authored
Morph msm_dsi_pll_save/restore_state() into msm_dsi_phy_save/restore_state(), thus removing last bits of knowledge about msm_dsi_pll from dsi_manager. Signed-off-by:
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Dmitry Baryshkov authored
Use devm_of_clk_add_hw_provider() to register provided clocks. This allows dropping the remove function alltogether. Signed-off-by:
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Dmitry Baryshkov authored
Use devres-enabled version of clock registration functions. This lets us remove dsi_pll destroy callbacks completely. Signed-off-by:
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Dmitry Baryshkov authored
All MSM DSI PHYs provide two clocks: byte and pixel ones. Register/unregister provided clocks from the generic place, removing boilerplate code from all MSM DSI PHY drivers. Signed-off-by:
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Dmitry Baryshkov authored
msm_dsi_pll_set_usecase() function is not used outside of individual DSI PHY drivers, so drop it in favour of calling the the respective set_usecase functions directly. Signed-off-by:
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Dmitry Baryshkov authored
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Dmitry Baryshkov authored
With the current upstream driver the msm_dsi_phy_type enum does not make much sense: all DSI PHYs are probed using the dt bindings, the phy type is not passed between drivers. Use quirks in phy individual PHY drivers to differentiate minor harware differences and drop the enum. Signed-off-by:
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Dmitry Baryshkov authored
Move all PLL-related callbacks into struct msm_dsi_phy_cfg. This limits the amount of data in the struct msm_dsi_pll. Signed-off-by:
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Dmitry Baryshkov authored
The only PLL using multiple enable sequences is the 28nm PLL, which just does the single step in the loop. Push that support back into the PLL code. Signed-off-by:
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Dmitry Baryshkov authored
Each phy version is tightly coupled with the corresponding PLL code, there is no need to keep them separate. Fuse source files together in order to simplify DSI code. Signed-off-by:
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Dmitry Baryshkov authored
DSI PHY init callback would either map dsi_phy_regulator or dsi_phy_lane depending on the PHY type. Replace those callbacks with configuration options governing mapping those regions. Signed-off-by:
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Dmitry Baryshkov authored
Add devm_clk_hw_register_divider() - devres version of clk_hw_register_divider(). Signed-off-by:
Stephen Boyd <sboyd@kernel.org> Link: https://lore.kernel.org/r/20210331105735.3690009-3-dmitry.baryshkov@linaro.org Signed-off-by:
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Dmitry Baryshkov authored
Add devm_clk_hw_register_mux() - devres-managed version of clk_hw_register_mux(). Signed-off-by:
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Abhinav Kumar authored
Currently the error checking logic in the dp_debug module could pass zero to PTR_ERR and it causes the below kbot warnings: drivers/gpu/drm/msm/dp/dp_debug.c:378 dp_debug_init() warn: passing zero to 'PTR_ERR' drivers/gpu/drm/msm/dp/dp_debug.c:387 dp_debug_init() warn: passing zero to 'PTR_ERR' drivers/gpu/drm/msm/dp/dp_debug.c:396 dp_debug_init() warn: passing zero to 'PTR_ERR' drivers/gpu/drm/msm/dp/dp_debug.c:405 dp_debug_init() warn: passing zero to 'PTR_ERR' Debugfs functions are not supposed to be checked in the normal case so delete this code. Also it silences the above Smatch warnings that we're checking for NULL when these functions only return error pointers. Reported-by:
kernel test robot <lkp@intel.com> Reported-by:
Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by:
Stephen Boyd <swboyd@chromium.org> Link: https://lore.kernel.org/r/1614971839-2686-3-git-send-email-abhinavk@codeaurora.org Signed-off-by:
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Abhinav Kumar authored
Fix an incorrect NULL check reported by kbot in the MSM DP driver smatch warnings: drivers/gpu/drm/msm/dp/dp_hpd.c:37 dp_hpd_connect() error: we previously assumed 'hpd_priv->dp_cb' could be null (see line 37) Reported-by:
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Abhinav Kumar authored
Fix a couple of indentation warnings reported by kbot across MSM DP driver: New smatch warnings: drivers/gpu/drm/msm/dp/dp_debug.c:229 dp_test_data_show() warn: inconsistent indenting drivers/gpu/drm/msm/dp/dp_power.c:203 dp_power_clk_enable() warn: inconsistent indenting Reported-by:
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AngeloGioacchino Del Regno authored
The MSM8996 core_mmss clock was commented out due to some strange issues that others were experiencing. At least SONY Tone family is working perfectly fine with this clock declared and gets it up and running without any error. Signed-off-by:
AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Signed-off-by:
Konrad Dybcio <konrad.dybcio@somainline.org> Link: https://lore.kernel.org/r/20210228124328.136397-1-konrad.dybcio@somainline.org Signed-off-by:
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Bhaskar Chowdhury authored
s/confguration/configuration/ s/Regsiters/Registers/ Signed-off-by:
Bhaskar Chowdhury <unixbhaskar@gmail.com> Link: https://lore.kernel.org/r/20210205084758.354509-1-unixbhaskar@gmail.com Signed-off-by:
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Bernard Zhao authored
Line 1826 pr_err is redundant because memory alloc already prints an error when failed. Signed-off-by:
Bernard Zhao <bernard@vivo.com> Link: https://lore.kernel.org/r/20210202120552.14744-1-bernard@vivo.com Signed-off-by:
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Kalyan Thota authored
Set the flag vblank_disable_immediate = true to turn off vblank irqs immediately as soon as drm_vblank_put is requested so that there are no irqs triggered during idle state. This will reduce cpu wakeups and help in power saving. To enable vblank_disable_immediate flag the underlying KMS driver needs to support high precision vblank timestamping and also a reliable way of providing vblank counter which is incrementing at the leading edge of vblank. This patch also brings in changes to support vblank_disable_immediate requirement in dpu driver. Changes in v1: - Specify reason to add vblank timestamp support. (Rob). - Add changes to provide vblank counter from dpu driver. Changes in v2: - Fix warn stack reported by Rob Clark with v2 patch. Changes in v3: - Move back to HW frame counter (Rob). Changes in v4: - Frame count mismatch was causing a DRM WARN stack spew. DPU HW will increment the frame count at the end of the sync, where as vblank will be triggered at the fetch_start counter which is calculated as v_total - vfp. This is to start fetching early for panels with low vbp w.r.t hw latency lines. Add logic to detect the line count if it falls between vactive and v_total then return incremented frame count value. Signed-off-by:
Kalyan Thota <kalyan_t@codeaurora.org> Link: https://lore.kernel.org/r/1613651746-12783-1-git-send-email-kalyan_t@codeaurora.org Signed-off-by:
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Rob Clark authored
Performance counts, and ALWAYS_ON counters used for capturing GPU timestamps, lose their state across suspend/resume cycles. Userspace tooling for performance monitoring needs to be aware of this. For example, after a suspend userspace needs to recalibrate it's offset between CPU and GPU time. Signed-off-by:
Jordan Crouse <jordan@cosmicpenguin.net> Link: https://lore.kernel.org/r/20210325012358.1759770-3-robdclark@gmail.com Signed-off-by:
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Akhil P Oommen authored
The speedbin support requires nvmem driver api. So lets explicitly enable CONFIG_NVMEM to have this support. Signed-off-by:
Akhil P Oommen <akhilpo@codeaurora.org> Link: https://lore.kernel.org/r/1617630433-36506-2-git-send-email-akhilpo@codeaurora.org Signed-off-by:
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Akhil P Oommen authored
We were not programing the correct bit while clearing the perfcounter oob. So, clear it correctly using the new 'clear' bit. This fixes the below error: [drm:a6xx_gmu_set_oob] *ERROR* Timeout waiting for GMU OOB set PERFCOUNTER: 0x80000000 Signed-off-by:
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Jonathan Marek authored
The driver already has support for sm8150/sm8250, but the compatibles were never added. Also inverse the non-mdp4 condition in add_display_components() to avoid having to check every new compatible in the condition. Signed-off-by:
Jonathan Marek <jonathan@marek.ca> Signed-off-by:
Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210329120051.3401567-4-dmitry.baryshkov@linaro.org Signed-off-by:
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