- Feb 27, 2020
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Evan Green authored
In some circumstances on Intel LPSS controllers, toggling the LPSS CS control register doesn't actually cause the CS line to toggle. This seems to be failure of dynamic clock gating that occurs after going through a suspend/resume transition, where the controller is sent through a reset transition. This ruins SPI transactions that either rely on delay_usecs, or toggle the CS line without sending data. Whenever CS is toggled, momentarily set the clock gating register to "Force On" to poke the controller into acting on CS. Signed-off-by:
Rajat Jain <rajatja@google.com> Signed-off-by:
Evan Green <evgreen@chromium.org> Link: https://lore.kernel.org/r/20200211223700.110252-1-rajatja@google.com Signed-off-by:
Mark Brown <broonie@kernel.org>
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- Feb 21, 2020
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Lukas Wunner authored
Commit f3186dd8 ("spi: Optionally use GPIO descriptors for CS GPIOs") amended of_spi_parse_dt() to always set SPI_CS_HIGH for SPI slaves whose Chip Select is defined by a "cs-gpios" devicetree property. This change broke userspace applications which issue an SPI_IOC_WR_MODE ioctl() to an spidev: Chip Select polarity will be incorrect unless the application is changed to set SPI_CS_HIGH. And once changed, it will be incompatible with kernels not containing the commit. Fix by setting SPI_CS_HIGH in spidev_ioctl() (under the same conditions as in of_spi_parse_dt()). Fixes: f3186dd8 ("spi: Optionally use GPIO descriptors for CS GPIOs") Reported-by:
Simon Han <z.han@kunbus.com> Signed-off-by:
Lukas Wunner <lukas@wunner.de> Reviewed-by:
Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/fca3ba7cdc930cd36854666ceac4fbcf01b89028.1582027457.git.lukas@wunner.de Signed-off-by:
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Yuji Sasaki authored
spi_qup_suspend() will cause synchronous external abort when runtime suspend is enabled and applied, as it tries to access SPI controller register while clock is already disabled in spi_qup_pm_suspend_runtime(). Signed-off-by:
Yuji sasaki <sasakiy@chromium.org> Signed-off-by:
Vinod Koul <vkoul@kernel.org> Link: https://lore.kernel.org/r/20200214074340.2286170-1-vkoul@kernel.org Signed-off-by:
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- Feb 06, 2020
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Vignesh Raghavendra authored
dma_request_channel() can return -EPROBE_DEFER, if DMA driver is not ready. Currently driver just falls back to PIO mode on probe deferral. Fix this by requesting all required channels during probe and propagating EPROBE_DEFER error code. Signed-off-by:
Vignesh Raghavendra <vigneshr@ti.com> Link: https://lore.kernel.org/r/20200204124816.16735-3-vigneshr@ti.com Signed-off-by:
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Vignesh Raghavendra authored
On AM654, McSPI can only support 4K - 1 bytes per transfer when DMA is enabled. Therefore populate master->max_transfer_size callback to inform client drivers of this restriction when DMA channels are available. Signed-off-by:
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- Jan 23, 2020
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Tomer Maimon authored
Add NPCM Peripheral SPI reset binding documentation, Removing unnecessary aliases use. Signed-off-by:
Tomer Maimon <tmaimon77@gmail.com> Acked-by:
Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20200115162301.235926-4-tmaimon77@gmail.com Signed-off-by:
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- Jan 17, 2020
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Tomer Maimon authored
Modify NPCM perphiral SPI reset support from direct register access to reset controller support. Signed-off-by:
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Tomer Maimon authored
Improving spi 8 bit per word mode transfer performance by using 16 bit per word transfer and receive when the data length is even and larger than one. Signed-off-by:
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Jean Pihet authored
drivers/spi/spi-ti-qspi.c: In function ‘ti_qspi_start_transfer_one’: drivers/spi/spi-ti-qspi.c:392:8: warning: ‘rx_wlen’ may be used uninitialized in this function [-Wmaybe-uninitialized] 392 | if (rx_wlen >= 32) | ^ drivers/spi/spi-ti-qspi.c:318:12: note: ‘rx_wlen’ was declared here 318 | u8 rxlen, rx_wlen; | ^~~~~~~ The warning is a false positive; it is not thrown by all compiler versions, e.g. Red Hat Cross 9.2.1-1 but not Linaro GCC 7.5-2019.12. Signed-off-by:Jean Pihet <jean.pihet@newoldbits.com> Link: https://lore.kernel.org/r/20200115100700.3357-1-jean.pihet@newoldbits.com Signed-off-by:
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- Jan 15, 2020
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Christophe Leroy authored
No need to 'goto err;' for just doing a return. return directly from where the error happens. Signed-off-by:
Christophe Leroy <christophe.leroy@c-s.fr> Link: https://lore.kernel.org/r/2a4a7e11b37cfa0558d68f0d35e90d6da858b059.1579017697.git.christophe.leroy@c-s.fr Signed-off-by:
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Philippe Schenker authored
Why it does not work at the moment: - num_chipselect sets the number of cs-gpios that are in the DT. This comes from drivers/spi/spi.c - num_chipselect gets set with devm_spi_register_controller, that is called in drivers/spi/spi.c - devm_spi_register_controller got called after num_chipselect has been used. How this commit fixes the issue: - devm_spi_register_controller gets called before num_chipselect is being used. Fixes: c7a40259 ("spi: lpspi: use the core way to implement cs-gpio function") Signed-off-by:
Philippe Schenker <philippe.schenker@toradex.com> Link: https://lore.kernel.org/r/20191204141312.1411251-1-philippe.schenker@toradex.com Signed-off-by:
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- Jan 14, 2020
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Jean Pihet authored
Optimize the 8-bit based transfers, as used by the SPI flash devices, by reading the data registers by 32 and 128 bits when possible and copy the contents to the receive buffer. The speed improvement is 4.9x using quad read. Signed-off-by:
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Jean Pihet authored
The TI QSPI IP has limitations: - the MMIO region is 64MB in size - in non-MMIO mode, the transfer can handle 4096 words max. Add support for bigger devices. Use MMIO and DMA transfers below the 64MB boundary, use software generated transfers above. Signed-off-by:
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- Jan 13, 2020
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Matthias Kaehlcke authored
Currrently the memory for the clk_bulk_data of the QSPI controller is allocated with spi_alloc_master(). The bulk data pointer is passed to devm_clk_bulk_get() which saves it in clk_bulk_devres->clks. When the device is removed later devm_clk_bulk_release() is called and uses the bulk data referenced by the pointer to release the clocks. For this driver this results in accessing memory that has already been freed, since the memory allocated with spi_alloc_master() is released by spi_controller_release(), which is called before the managed resources are released. Use device managed memory for the clock bulk data to fix the issue described above. Signed-off-by:
Matthias Kaehlcke <mka@chromium.org> Reviewed-by:
Douglas Anderson <dianders@chromium.org> Link: https://lore.kernel.org/r/20200108133948.1.I35ceb4db3ad8cfab78f7cd51494aeff4891339f5@changeid Signed-off-by:
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- Jan 10, 2020
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John Garry authored
Set John Garry @ Huawei as the maintainer. Signed-off-by:
John Garry <john.garry@huawei.com> Link: https://lore.kernel.org/r/1575900490-74467-4-git-send-email-john.garry@huawei.com Signed-off-by:
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John Garry authored
Add the driver for the HiSilicon v3xx SPI NOR flash controller, commonly found in hi16xx chipsets. This is a different controller than that in drivers/mtd/spi-nor/hisi-sfc.c; indeed, the naming for that driver is poor, since it is really known as FMC, and can support other memory technologies. The driver module name is "hisi-sfc-v3xx", as recommended by HW designer, being an attempt to provide a distinct name - v3xx being the unique controller versioning. Only ACPI firmware is supported. DMA is not supported, and we just use polling mode for operation completion notification. The driver uses the SPI MEM OPs. Signed-off-by:
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Claudiu Beznea authored
Add microchip,sam9x60-spi to DT bindings documentation. Signed-off-by:
Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/1578488123-26127-13-git-send-email-claudiu.beznea@microchip.com Signed-off-by:
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Lukas Wunner authored
The "RevPi Connect Flat" PLC offered by KUNBUS has 4 slaves attached to the BCM2835 SPI master. Raise the maximum number of slaves in the driver accordingly. Signed-off-by:
Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Link: https://lore.kernel.org/r/01453fd062de2d49bd74a847e13a0781cbf8143d.1578572268.git.lukas@wunner.de Signed-off-by:
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- Jan 09, 2020
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Krzysztof Kozlowski authored
STR is a well-known stringify macro so it should be avoided in drivers to avoid warnings like this (MIPS architecture while compile testing): drivers/spi/spi-sh-msiof.c:76:0: warning: "STR" redefined #define STR 0x40 /* Status Register */ arch/mips/include/asm/mipsregs.h:30:0: note: this is the location of the previous definition #define STR(x) __STR(x) To maintain consistency between all register names add a SI prefix to all of them. This also matches register names in datasheet. Signed-off-by:Krzysztof Kozlowski <krzk@kernel.org> Reviewed-by:
Geert Uytterhoeven <geert+renesas@glider.be> Tested-by:
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- Jan 08, 2020
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Geert Uytterhoeven authored
Add support for GPIO chip selects using GPIO descriptors. As the RSPI controller always drives a native chip select when performing a transfer, at least one native chip select must be left unused. Signed-off-by:
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Geert Uytterhoeven authored
RSPI variants on some SuperH or R-Mobile SoCs support multiple native chip selects. Add support for this by configuring the SSL Assert Signal Setting. Signed-off-by:
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Geert Uytterhoeven authored
The set_config_register() macro is used in a single place. Make the code easier to read by just removing it. Signed-off-by:
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Geert Uytterhoeven authored
Use the helper introduced by commit e135303b ("device: Add dev_<level>_once variants") instead of open-coding the same operation. Signed-off-by:
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Geert Uytterhoeven authored
Currently the MSIOF SPI driver uses custom code to handle the unused native chip select with GPIO chip selects. Convert the driver to use the new generic handling in the SPI core. Signed-off-by:
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Geert Uytterhoeven authored
Some SPI master controllers always drive a native chip select when performing a transfer. Hence when using both native and GPIO chip selects, at least one native chip select must be left unused, to be driven when performing transfers with slave devices using GPIO chip selects. Currently, to find an unused native chip select, SPI controller drivers need to parse and process cs-gpios theirselves. This is not only duplicated in each driver that needs it, but also duplicates part of the work done later at SPI controller registration time. Note that this cannot be done after spi_register_controller() returns, as at that time, slave devices may have been probed already. Hence add generic support to the SPI subsystem for finding an unused native chip select. Optionally, this unused native chip select, and all other in-use native chip selects, can be validated against the maximum number of native chip selects available on the controller hardware. Signed-off-by:
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Rayagonda Kokatanur authored
Use platform_get_irq_byname_optional() instead of platform_get_irq_byname() to avoid below error message during probe: [3.265115] bcm_iproc 68c70200.spi: IRQ spi_lr_fullness_reached not found [3.272121] bcm_iproc 68c70200.spi: IRQ spi_lr_session_aborted not found [3.284965] bcm_iproc 68c70200.spi: IRQ spi_lr_impatient not found [3.291344] bcm_iproc 68c70200.spi: IRQ spi_lr_session_done not found [3.297992] bcm_iproc 68c70200.spi: IRQ mspi_done not found [3.303742] bcm_iproc 68c70200.spi: IRQ mspi_halted not found Signed-off-by:
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> Link: https://lore.kernel.org/r/20200107040912.16426-1-rayagonda.kokatanur@broadcom.com Signed-off-by:
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- Dec 28, 2019
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Vladimir Oltean authored
We can catch whether the SPI controller has declared it can take care of software timestamping transfers, but didn't. So do it. Signed-off-by:
Vladimir Oltean <olteanv@gmail.com> Link: https://lore.kernel.org/r/20191227012444.1204-1-olteanv@gmail.com Signed-off-by:
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- Dec 27, 2019
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Linus Walleij authored
Switch the OC Tiny driver over to handling CS GPIOs using GPIO descriptors in the core. This driver is entirely relying on GPIOs to be used for chipselect, so let the core pick these out using either device tree or machine descriptors. There are no in-tree users of this driver so no board files need to be patched, out-of-tree boardfiles can use machine descriptor tables, c.f. commit 1dfbf334 . Cc: Thomas Chou <thomas@wytron.com.tw> Signed-off-by:
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- Dec 26, 2019
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Kunihiko Hayashi authored
This adds DMA transfer mode support for UniPhier SPI controller. Since this controller requires simulteaneous transmission and reception, this indicates SPI_CONTROLLER_MUST_RX and SPI_CONTROLLER_MUST_TX. Because the supported dma controller has alignment restiction, there is also a restriction that 'maxburst' parameters in dma_slave_config corresponds to one word width. Signed-off-by:
Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Link: https://lore.kernel.org/r/1577149107-30670-6-git-send-email-hayashi.kunihiko@socionext.com Signed-off-by:
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zhengbin authored
Fixes coccicheck warning: drivers/spi/spi-tegra114.c:272:2-17: WARNING: Assignment of 0/1 to bool variable drivers/spi/spi-tegra114.c:275:2-17: WARNING: Assignment of 0/1 to bool variable Reported-by:
Hulk Robot <hulkci@huawei.com> Signed-off-by:
zhengbin <zhengbin13@huawei.com> Link: https://lore.kernel.org/r/1577159526-33689-4-git-send-email-zhengbin13@huawei.com Signed-off-by:
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zhengbin authored
Fixes coccicheck warning: drivers/spi/spi-imx.c:1233:2-17: WARNING: Assignment of 0/1 to bool variable drivers/spi/spi-imx.c:1235:2-17: WARNING: Assignment of 0/1 to bool variable Reported-by:
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zhengbin authored
Fixes coccicheck warning: drivers/spi/spi-fsl-lpspi.c:472:2-19: WARNING: Assignment of 0/1 to bool variable drivers/spi/spi-fsl-lpspi.c:474:2-19: WARNING: Assignment of 0/1 to bool variable Reported-by:
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- Dec 25, 2019
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Kunihiko Hayashi authored
This adds master->handle_err() callback function to stop transfer due to error. The function also resets FIFOs and disables interrupt. Signed-off-by:
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Kunihiko Hayashi authored
This changes each argument of functions uniphier_irq_{enable,disable}() to uniphier_spi_priv because these functions are used not only for spi_device but also for the entire controller. Signed-off-by: -
Kunihiko Hayashi authored
Rx threshold means the value to inform the receiver when the number of words in Rx FIFO is equal to or more than the value. Similarly, Tx threshold means the value to inform the sender when the number of words in Tx FIFO is equal to or less than the value. The controller triggers the driver to start the transfer. In case of Rx, the driver wants to detect that the specified number of words N are in Rx FIFO, so the value of Rx threshold should be N. In case of Tx, the driver wants to detect that the same number of spaces as Rx are in Tx FIFO, so the value of Tx threshold should be (FIFO size - N). For example, in order for the driver to receive at least 3 words from Rx FIFO, set 3 to Rx threshold. +-+-+-+-+-+-+-+-+ | | | | | |*|*|*| +-+-+-+-+-+-+-+-+ In order for the driver to send at least 3 words to Tx FIFO, because it needs at least 3 spaces, set 8(FIFO size) - 3 = 5 to Tx threshold. +-+-+-+-+-+-+-+-+ |*|*|*|*|*| | | | +-+-+-+-+-+-+-+-+ This adds new function uniphier_spi_set_fifo_threshold() to set threshold value to the register. And more, FIFO counts by 'words', so this renames 'fill_bytes' with 'fill_words', and fixes the calculation using bytes_per_words. Fixes: 37ffab81 ("spi: uniphier: introduce polling mode") Cc: Keiji Hayashibara <hayashibara.keiji@socionext.com> Signed-off-by:
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- Dec 19, 2019
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Benjamin Gaignard authored
Convert the STM32 spi binding to DT schema format using json-schema Signed-off-by:
Benjamin Gaignard <benjamin.gaignard@st.com> CC: Erwan Leray <erwan.leray@st.com> CC: Fabrice Gasnier <fabrice.gasnier@st.com> CC: Amelie Delaunay <amelie.delaunay@st.com> Reviewed-by:
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- Dec 17, 2019
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Jim Quinlan authored
Use dev_dbg() on -EPROBE_DEFER and dev_err() on all other errors. Signed-off-by:
Jim Quinlan <jquinlan@broadcom.com> Reviewed-by:
Florian Fainelli <f.fainelli@gmail.com> Reviewed-by:
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Jean Pihet authored
The fclk and its rate are retrieved from DT. Signed-off-by:
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- Dec 16, 2019
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Linus Walleij authored
Instead of grabbing GPIOs using the legacy interface and handling them in the setup callback, just let the core grab and use the GPIOs using descriptors. Cc: Neil Armstrong <narmstrong@baylibre.com> Cc: Sunny Luo <sunny.luo@amlogic.com> Signed-off-by:
Neil Armstrong <narmstrong@baylibre.com> Link: https://lore.kernel.org/r/20191205083915.27650-1-linus.walleij@linaro.org Signed-off-by:
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