- Feb 24, 2023
-
-
Stephen Boyd authored
Merge branches 'clk-microchip', 'clk-allwinner', 'clk-mediatek', 'clk-imx' and 'clk-core' into clk-next - Various cleanups and improvements to Mediatek clk drivers to reduce code size and modernize the drivers - Support for Mediatek MT7891 SoC clks * clk-microchip: clk: at91: do not compile dt-compat.c for sama7g5 and sam9x60 clk: at91: mark ddr clocks as critical * clk-allwinner: clk: sunxi-ng: d1: Add CAN bus gates and resets dt-bindings: clock: Add D1 CAN bus gates and resets clk: sunxi-ng: d1: Mark cpux clock as critical clk: sunxi-ng: d1: Allow building for R528/T113 clk: sunxi-ng: Move SoC driver conditions to dependencies clk: sunxi-ng: Remove duplicate ARCH_SUNXI dependencies clk: sunxi-ng: Avoid computing the rate twice clk: sunxi-ng: h3/h5: Model H3 CLK_DRAM as a fixed clock clk: sunxi-ng: fix ccu_mmc_timing.c kernel-doc issues * clk-mediatek: (29 commits) clk: mediatek: clk-mtk: Remove unneeded semicolon clk: mediatek: remove MT8195 vppsys/0/1 simple_probe dt-bindings: arm: mediatek: migrate MT8195 vppsys0/1 to mtk-mmsys driver clk: mediatek: add MT7981 clock support dt-bindings: clock: mediatek: add mt7981 clock IDs dt-bindings: clock: Add compatibles for MT7981 clk: mediatek: clk-mt7986-topckgen: Migrate to mtk_clk_simple_probe() clk: mediatek: clk-mt7986-topckgen: Properly keep some clocks enabled clk: mediatek: clk-mt6795-topckgen: Migrate to mtk_clk_simple_probe() clk: mediatek: clk-mt8186-topckgen: Migrate to mtk_clk_simple_probe() clk: mediatek: clk-mt8192: Migrate topckgen to mtk_clk_simple_probe() clk: mediatek: clk-mtk: Register MFG notifier in mtk_clk_simple_probe() clk: mediatek: clk-mt8183: Join top_aud_muxes and top_aud_divs clk: mediatek: mt8186: Join top_adj_div and top_muxes clk: mediatek: mt8192: Join top_adj_divs and top_muxes clk: mediatek: clk-mt8192: Move CLK_TOP_CSW_F26M_D2 in top_divs clk: mediatek: mt8173: Migrate pericfg/topckgen to mtk_clk_simple_probe() clk: mediatek: clk-mtk: Extend mtk_clk_simple_probe() clk: mediatek: Switch to mtk_clk_simple_probe() where possible clk: mediatek: mt8173: Break down clock drivers and allow module build ... * clk-imx: clk: imx: pll14xx: fix recalc_rate for negative kdiv MAINTAINERS: clk: imx: Add Peng Fan as reviewer clk: imx: fix compile testing imxrt1050 clk: imx: set imx_clk_gpr_mux_ops storage-class-specifier to static clk: imx6ul: add ethernet refclock mux support clk: imx6ul: fix enet1 gate configuration clk: imx: add imx_obtain_fixed_of_clock() clk: imx6q: add ethernet refclock mux support clk: imx: add clk-gpr-mux driver dt-bindings: imx8ulp: clock: no spaces before tabs clk: imx6sll: add proper spdx license identifier clk: imx: imx93: invoke imx_register_uart_clocks clk: imx: remove clk_count of imx_register_uart_clocks clk: imx: get stdout clk count from device tree clk: imx: avoid memory leak * clk-core: clk: Honor CLK_OPS_PARENT_ENABLE in clk_core_is_enabled()
-
Stephen Boyd authored
Merge branches 'clk-cleanup', 'clk-bindings', 'clk-renesas', 'clk-versa' and 'clk-amlogic' into clk-next - Support for Versa 5P49V60 clks * clk-cleanup: clk: rs9: Drop unused pin_xin field clk: sprd: Add dependency for SPRD_UMS512_CLK clk: ralink: fix 'mt7621_gate_is_enabled()' function dt-bindings: clock: remove stih416 bindings drivers/clk: Remove "select SRCU" * clk-bindings: dt-bindings: clock: qcom,sm8450-camcc: constrain required-opps dt-bindings: clock: imx8m-clock: correct i.MX8MQ node name * clk-renesas: clk: renesas: rcar-gen3: Disable R-Car H3 ES1.* clk: renesas: r8a779g0: Add CAN-FD clocks clk: renesas: r8a779g0: Tidy up DMAC name on SYS-DMAC clk: renesas: r8a779a0: Tidy up DMAC name on SYS-DMAC clk: renesas: r8a779g0: Add custom clock for PLL2 clk: renesas: cpg-mssr: Remove superfluous check in resume code clk: renesas: r9a06g032: Handle h2mode setting based on USBF presence clk: renesas: cpg-mssr: Fix use after free if cpg_mssr_common_init() failed clk: renesas: r9a07g044: Add clock and reset entries for CRU clk: renesas: r9a09g011: Add SDHI/eMMC clock and reset entries clk: renesas: r9a09g011: Add USB clock and reset entries clk: renesas: r9a09g011: Add TIM clock and reset entries clk: renesas: r8a779g0: Add display related clocks clk: renesas: rcar-gen4: Restore PLL enum sort order clk: renesas: r8a779g0: Fix OSC predividers clk: renesas: r9a09g011: Add PWM clock and reset entries * clk-versa: dt-bindings: clock: versaclock5: Document 5P49V60 compatible string clk: vc5: Add support for 5P49V60 clk: vc5: Use `clamp()` to restrict PLL range * clk-amlogic: clk: meson: clk-cpu-dyndiv: switch from .round_rate to .determine_rate clk: meson: sclk-div: switch from .round_rate to .determine_rate clk: meson: dualdiv: switch from .round_rate to .determine_rate clk: meson: mpll: Switch from .round_rate to .determine_rate
-
- Feb 22, 2023
-
-
Kevin Groeneveld authored
kdiv is a signed 16 bit value in the DEV_CTL1 register. Commit 53990cf9 ("clk: imx: pll14xx: consolidate rate calculation") changed the kdiv variable from a short int to just int. When the value read from the DIV_CTL1 register is assigned directly to an int the sign of the value is lost resulting in incorrect results when the value is negative. Adding a s16 cast to the register value fixes the issue. Fixes: 53990cf9 ("clk: imx: pll14xx: consolidate rate calculation") Signed-off-by:
Kevin Groeneveld <kgroeneveld@lenbrook.com> Link: https://lore.kernel.org/r/20221210203835.9714-1-kgroeneveld@lenbrook.com Reviewed-by:
Abel Vesa <abel.vesa@linaro.org> Signed-off-by:
Stephen Boyd <sboyd@kernel.org>
-
- Feb 18, 2023
-
-
Marek Vasut authored
The pin_xin field in struct rs9_driver_data is unused, drop it. Signed-off-by:
Marek Vasut <marex@denx.de> Link: https://lore.kernel.org/r/20221216210922.592926-1-marex@denx.de Reviewed-by:
Alexander Stein <alexander.stein@ew.tq-group.com> Signed-off-by:
-
Abel Vesa authored
Peng Fan will step up to help with reviewing. Add his email to the i.MX clocks drivers entry. Cc: Peng Fan <peng.fan@nxp.com> Signed-off-by:
Peng Fan <peng.fan@nxp.com>:> Signed-off-by:
-
- Feb 15, 2023
-
-
Stephen Boyd authored
Merge tag 'renesas-clk-for-v6.3-tag3' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas Pull one more Renesas clk driver update from Geert Uytterhoeven: - Disable R-Car H3 ES1.*, as it was only available to an internal development group and needed a lot of quirks and workarounds. * tag 'renesas-clk-for-v6.3-tag3' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers: clk: renesas: rcar-gen3: Disable R-Car H3 ES1.*
-
- Feb 11, 2023
-
-
Cixi Geng authored
Add depends on and default for ums512 clk config. Signed-off-by:
Cixi Geng <cixi.geng1@unisoc.com> Link: https://lore.kernel.org/r/20230201091300.3201-1-cixi.geng@linux.dev Signed-off-by:
-
Sergio Paracuellos authored
Compiling clock driver with CONFIG_UBSAN enabled shows the following trace: UBSAN: shift-out-of-bounds in drivers/clk/ralink/clk-mt7621.c:121:15 shift exponent 131072 is too large for 32-bit type 'long unsigned int' CPU: 1 PID: 1 Comm: swapper/0 Not tainted 5.15.86 #0 Stack : ... Call Trace: [<80009a58>] show_stack+0x38/0x118 [<8045ce04>] dump_stack_lvl+0x60/0x80 [<80458868>] ubsan_epilogue+0x10/0x54 [<804590e0>] __ubsan_handle_shift_out_of_bounds+0x118/0x190 [<804c9a10>] mt7621_gate_is_enabled+0x98/0xa0 [<804bb774>] clk_core_is_enabled+0x34/0x90 [<80aad73c>] clk_disable_unused_subtree+0x98/0x1e4 [<80aad6d4>] clk_disable_unused_subtree+0x30/0x1e4 [<80aad6d4>] clk_disable_unused_subtree+0x30/0x1e4 [<80aad900>] clk_disable_unused+0x78/0x120 [<80002030>] do_one_initcall+0x54/0x1f0 [<80a922a4>] kernel_init_freeable+0x280/0x31c [<808047c4>] kernel_init+0x20/0x118 [<80003e58>] ret_from_kernel_thread+0x14/0x1c Shifting a value (131032) larger than the type (32 bit unsigned integer) is undefined behaviour in C. The problem is in 'mt7621_gate_is_enabled()' function which is using the 'BIT()' kernel macro with the bit index for the clock gate to check if the bit is set. When the clock gates structure is created driver is already setting 'bit_idx' using 'BIT()' macro, so we are wrongly applying an extra 'BIT()' mask here. Removing it solve the problem and makes this function correct. However when clock gating is correctly working, the kernel starts disabling those clocks that are not requested. Some drivers for this SoC are older than this clock driver itself. So to avoid the kernel to disable clocks that have been enabled until now, we must apply 'CLK_IS_CRITICAL' flag on gates initialization code. Fixes: 48df7a26 ("clk: ralink: add clock driver for mt7621 SoC") Signed-off-by:
Sergio Paracuellos <sergio.paracuellos@gmail.com> Link: https://lore.kernel.org/r/20230206083305.147582-1-sergio.paracuellos@gmail.com Signed-off-by:
-
Yang Li authored
./drivers/clk/mediatek/clk-mtk.c:518:2-3: Unneeded semicolon Reported-by:
Abaci Robot <abaci@linux.alibaba.com> Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=3926 Signed-off-by:
Yang Li <yang.lee@linux.alibaba.com> Link: https://lore.kernel.org/r/20230202010750.79515-1-yang.lee@linux.alibaba.com Reviewed-by:
Matthias Brugger <matthias.bgg@gmail.com> Signed-off-by:
-
Alain Volmat authored
Remove the stih416 clock dt-bindings since this platform is no more supported. Signed-off-by:
Alain Volmat <avolmat@me.com> Link: https://lore.kernel.org/r/20230209091659.1409-11-avolmat@me.com Acked-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by:
-
Arnd Bergmann authored
Randconfig testing revealed multiple issues with this driver: ERROR: modpost: missing MODULE_LICENSE() in drivers/clk/imx/clk-imxrt1050.o ERROR: modpost: "imx_clk_hw_pllv3" [drivers/clk/imx/clk-imxrt1050.ko] undefined! ERROR: modpost: "imx_clk_hw_pfd" [drivers/clk/imx/clk-imxrt1050.ko] undefined! Export the necessary symbols from the core clk driver and add the license and author tags. To find this type of problem more easily in the future, also enable building on other platforms, as we do for the other i.MX clk drivers. Signed-off-by:
Arnd Bergmann <arnd@arndb.de> Link: https://lore.kernel.org/r/20221215165836.2136448-1-arnd@kernel.org Acked-by:
Jesse Taube <Mr.Bossman075@gmail.com> Reviewed-by:
-
Chen-Yu Tsai authored
In the previous commits that added CLK_OPS_PARENT_ENABLE, support for this flag was only added to rate change operations (rate setting and reparent) and disabling unused subtree. It was not added to the clock gate related operations. Any hardware driver that needs it for these operations will either see bogus results, or worse, hang. This has been seen on MT8192 and MT8195, where the imp_ii2_* clk drivers set this, but dumping debugfs clk_summary would cause it to hang. Prepare parent on prepare and enable parent on enable dependencies are already handled automatically by the core as part of its sequencing. Whether the case for "enable parent on prepare" should be supported by this flag or not is not clear, and thus ignored for now. This change solely fixes the handling of clk_core_is_enabled, i.e. enabling the parent clock when reading the hardware state. Unfortunately clk_core_is_enabled is called in a variety of places, sometimes with the enable clock already held. To avoid deadlocking, the core will ignore readouts and just return false if CLK_OPS_PARENT_ENABLE is set but the parent isn't currently enabled. Fixes: fc8726a2 ("clk: core: support clocks which requires parents enable (part 2)") Fixes: a4b3518d ("clk: core: support clocks which requires parents enable (part 1)") Signed-off-by:
Chen-Yu Tsai <wenst@chromium.org> Link: https://lore.kernel.org/r/20230103092330.494102-1-wenst@chromium.org Tested-by:
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by:
-
Tom Rix authored
smatch reports drivers/clk/imx/clk-gpr-mux.c:73:22: warning: symbol 'imx_clk_gpr_mux_ops' was not declared. Should it be static? imx_clk_gpr_mux_ops is only used in clk-gpr-mux.c, so it should be static. Signed-off-by:
Tom Rix <trix@redhat.com> Link: https://lore.kernel.org/r/20230205030138.1723614-1-trix@redhat.com Fixes: ee394f63 ("clk: imx: add clk-gpr-mux driver") Signed-off-by:
-
Stephen Boyd authored
Merge tag 'clk-imx-6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/abelvesa/linux into clk-imx Pull i.MX clk driver updates from Abel Vesa: - Free the imx_uart_clocks even if imx_register_uart_clocks returns early - Get the stdout clocks count from device tree - Drop the clock count argument from imx_register_uart_clocks. - Keep the uart clocks on i.MX93 for when earlycon is used - Fix SPDX comment in i.MX6SLL clocks bindings header - Drop some unnecessary spaces from i.MX8ULP clocks bindings header - Add a new clk-gpr-mux clock type and use it on i.MX6Q to add ENET ref clocks - Add the imx_obtain_fixed_of_clock for allowing to add a clock that is not configured via devicetree - Fix the ENET1 gate configuration for i.MX6UL according to the reference manual - Add ENET refclock mux support for i.MX6UL * tag 'clk-imx-6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/abelvesa/linux: clk: imx6ul: add ethernet refclock mux support clk: imx6ul: fix enet1 gate configuration clk: imx: add imx_obtain_fixed_of_clock() clk: imx6q: add ethernet refclock mux support clk: imx: add clk-gpr-mux driver dt-bindings: imx8ulp: clock: no spaces before tabs clk: imx6sll: add proper spdx license identifier clk: imx: imx93: invoke imx_register_uart_clocks clk: imx: remove clk_count of imx_register_uart_clocks clk: imx: get stdout clk count from device tree clk: imx: avoid memory leak
-
- Feb 10, 2023
-
-
Wolfram Sang authored
R-Car H3 ES1.* was only available to an internal development group and needed a lot of quirks and workarounds. These become a maintenance burden now, so our development group decided to remove upstream support for this SoC. Public users only have ES2 onwards. In addition to the ES1 specific removals, a check for it was added preventing the machine to boot further. It may otherwise inherit wrong clock settings from ES2 which could damage the hardware. Signed-off-by:
Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by:
Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230202092332.2504-1-wsa+renesas@sang-engineering.com Signed-off-by:
-
- Feb 01, 2023
-
-
Moudy Ho authored
MT8195 VPPSYS0/1 will be probed by the compatible name in the mtk-mmsys driver and then probe its own clock driver as a platform driver. Signed-off-by:
Moudy Ho <moudy.ho@mediatek.com> Link: https://lore.kernel.org/r/20230118031509.29834-4-moudy.ho@mediatek.com Signed-off-by:
-
- Jan 31, 2023
-
-
Oleksij Rempel authored
Add ethernet refclock mux support and set it to internal clock by default. This configuration will not affect existing boards. clock tree before this patch: fec1 <- enet1_ref_125m (gate) <- enet1_ref (divider) <-, |- pll6_enet fec2 <- enet2_ref_125m (gate) <- enet2_ref (divider) <-´ after this patch: fec1 <- enet1_ref_sel(mux) <- enet1_ref_125m (gate) <- ... `--<> enet1_ref_pad |- pll6_enet fec2 <- enet2_ref_sel(mux) <- enet2_ref_125m (gate) <- ... `--<> enet2_ref_pad Signed-off-by:Oleksij Rempel <o.rempel@pengutronix.de> Acked-by:
Lee Jones <lee@kernel.org> Reviewed-by:
-
Oleksij Rempel authored
According to the "i.MX 6UltraLite Applications Processor Reference Manual, Rev. 2, 03/2017", BIT(13) is ENET1_125M_EN which is not controlling root of PLL6. It is controlling ENET1 separately. So, instead of this picture (implementation before this patch): fec1 <- enet_ref (divider) <---------------------------, |- pll6_enet (gate) fec2 <- enet2_ref_125m (gate) <- enet2_ref (divider) <-´ we should have this one (after this patch): fec1 <- enet1_ref_125m (gate) <- enet1_ref (divider) <-, |- pll6_enet fec2 <- enet2_ref_125m (gate) <- enet2_ref (divider) <-´ With this fix, the RMII reference clock will be turned off, after setting network interface down on each separate interface (ip l s dev eth0 down). Which was not working before, on system with both FECs enabled. Signed-off-by: -
Oleksij Rempel authored
Add imx_obtain_fixed_of_clock() to optionally add clock not configured in the devicetree. Signed-off-by:
-
Oleksij Rempel authored
Add ethernet refclock mux support and set it to internal clock by default. This configuration will not affect existing boards since machine code currently overwrites this default. The machine code will be fixed in a separate patch. Signed-off-by:
-
Oleksij Rempel authored
Almost(?) every i.MX variant has clk mux for ethernet (rgmii/rmii) reference clock located in the GPR1 register. So far this clk is configured in different ways: - mach-imx6q is doing mux configuration based on ptp vs enet_ref clk comparison. - mach-imx7d is setting mux to PAD for all boards - mach-imx6ul is setting mux to internal clock for all boards. Since we have imx7d and imx6ul board variants which do not work with configurations forced by kernel mach code, we need to implement this clk mux properly as part of the clk framework. Which is done by this patch. Signed-off-by:
-
Moudy Ho authored
MT8195 VPPSYS 0/1 should be probed from mtk-mmsys driver to populate device by platform_device_register_data then start its own clock driver. Signed-off-by:
-
Daniel Golle authored
Add MT7981 clock support, include topckgen, apmixedsys, infracfg and ethernet subsystem clocks. The drivers are based on clk-mt7981.c which can be found in MediaTek's SDK sources. To be fit for upstream inclusion the driver has been split into clock domains and the infracfg part has been significantly de-bloated by removing all the 1:1 factors (aliases). Signed-off-by:
Jianhui Zhao <zhaojh329@gmail.com> Signed-off-by:
Daniel Golle <daniel@makrotopia.org> Link: https://lore.kernel.org/r/8136eb5b2049177bc2f6d3e0f2aefecc342d626f.1674703830.git.daniel@makrotopia.org Reviewed-by:
-
Daniel Golle authored
Add MT7981 clock dt-bindings, include topckgen, apmixedsys, infracfg, and ethernet subsystem clocks. Acked-by:
-
Daniel Golle authored
Add compatible string for MT7981 to existing bindings at - mediatek,apmixedsys.yaml - mediatek,topckgen.yaml - mediatek,ethsys.txt - mediatek,infracfg.yaml - mediatek,sgmiisys.txt Signed-off-by:
-
AngeloGioacchino Del Regno authored
There are no more non-common calls in clk_mt7986_topckgen_probe(): migrate this driver to mtk_clk_simple_probe(). Signed-off-by:
Miles Chen <miles.chen@mediatek.com> Reviewed-by:
Mingming Su <mingming.su@mediatek.com> Signed-off-by:
-
AngeloGioacchino Del Regno authored
Instead of calling clk_prepare_enable() on a bunch of clocks at probe time, set the CLK_IS_CRITICAL flag to the same as these are required to be always on, and this is the right way of achieving that. Signed-off-by:
-
AngeloGioacchino Del Regno authored
Migrate away from custom probe functions and use the commonized mtk_clk_simple_{probe, remove}(). Signed-off-by: -
AngeloGioacchino Del Regno authored
As done with MT8192, migrate MT8186 topckgen away from a custom probe function and use mtk_clk_simple_{probe, remove}(). Signed-off-by: -
AngeloGioacchino Del Regno authored
Since the common simple probe function for MediaTek clock drivers can now register the MFG MUX notifier, it's possible to migrate MT8192's topckgen to that, allowing for some code size reduction. Signed-off-by:
-
AngeloGioacchino Del Regno authored
In preparation for commonizing topckgen probe on various MediaTek SoCs clock drivers, add the ability to register the MFG MUX notifier in mtk_clk_simple_probe() by passing a custom notifier register function pointer, as this function will be slightly different across different SoCs. Signed-off-by:
-
AngeloGioacchino Del Regno authored
Join the two to register them in one shot. Signed-off-by:
-
AngeloGioacchino Del Regno authored
Like done for MT8192, join the two to register them in one shot, as there's no point in doing that separately from one another. Signed-off-by:
-
AngeloGioacchino Del Regno authored
These two are both mtk_composite arrays, one dependent on another, but that's something that the clock framework is supposed to sort out and anyway registering them separately isn't going to ease the framework's job in checking dependencies. Put the contents of top_adj_divs in top_muxes to join them together and register them in one shot. Signed-off-by:
-
AngeloGioacchino Del Regno authored
This driver is registered early in clk_mt8192_top_init_early() and then again in clk_mt8192_top_probe(): the difference between the two is that the early one is probed with CLK_OF_DECLARE_DRIVER and the latter is regularly probed as a platform_driver. Knowing that it is not necessary for this platform to register the TOP_CSW_F26M_D2 clock that early, move it to top_divs and register it with the others during platform_driver probe for topckgen; While at it, since the only reason why the early probe existed was to register that clock, remove that entirely - leaving this driver to use only platform_driver. Signed-off-by:
-
AngeloGioacchino Del Regno authored
Function mtk_clk_simple_probe() gained the ability to register multiple clock types: migrate MT8173's pericfg and topckgen to this common probe function to reduce duplication and code size. Signed-off-by:
-
AngeloGioacchino Del Regno authored
As a preparation to increase probe functions commonization across various MediaTek SoC clock controller drivers, extend function mtk_clk_simple_probe() to be able to register not only gates, but also fixed clocks, factors, muxes and composites. Signed-off-by:
-
AngeloGioacchino Del Regno authored
mtk_clk_simple_probe() is a function that registers mtk gate clocks and, if reset data is present, a reset controller and across all of the MTK clock drivers, such a function is duplicated many times: switch to the common mtk_clk_simple_probe() function for all of the clock drivers that are registering as platform drivers. Signed-off-by:
-
AngeloGioacchino Del Regno authored
Split the giant clock driver for MT8173 into smaller drivers and make it possible to build the non boot critical clock controller drivers as modules by adding remove functions and both module description and license where needed. While at it, also change a mtk_register_reset_controller() call to mtk_register_reset_controller_with_dev() in mt8173-infracfg. Some spare code style cleanups were also performed. Signed-off-by:
-
AngeloGioacchino Del Regno authored
The entire point of mtk_clk_enable_critical() is to raise the refcount of some clocks so that they won't be turned off during runtime, but this is the same as what the CLK_IS_CRITICAL flag does. Set CLK_IS_CRITICAL on all of the critical clocks and remove the aforementioned function as a cleanup. No functional changes. Signed-off-by:
-
