- Jan 12, 2022
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Nirmoy Das authored
Get rid off pin/unpin of gart BO at resume/suspend and instead pin only once and try to recover gart content at resume time. This is much more stable in case there is OOM situation at 2nd call to amdgpu_device_evict_resources() while evicting GART table. v3: remove gart recovery from other places v2: pin gart at amdgpu_gart_table_vram_alloc() Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
Nirmoy Das <nirmoy.das@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Nirmoy Das authored
Do not allow exported amdgpu_vram_mgr_*() to accept any ttm_resource_manager pointer. Also there is no need to force other module to call a ttm function just to eventually call vram_mgr functions. v2: pass adev's vram_mgr instead of adev Reviewed-by:
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Nirmoy Das authored
Remove unused amdgpu_amdkfd_get_vram_usage() CC: Felix.Kuehling@amd.com Signed-off-by:
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Nirmoy Das authored
Do not allow exported amdgpu_gtt_mgr_*() to accept any ttm_resource_manager pointer. Also there is no need to force other module to call a ttm function just to eventually call gtt_mgr functions. v4: remove unused adev. v3: upcast mgr from ttm resopurce manager instead of getting it from adev. v2: pass adev's gtt_mgr instead of adev. Reviewed-by:
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Leslie Shi authored
Patch: 3efb17ae7e92 ("drm/amdgpu: Call amdgpu_device_unmap_mmio() if device is unplugged to prevent crash in GPU initialization failure") makes call to amdgpu_device_unmap_mmio() conditioned on device unplugged. This patch unmaps MMIO mappings even when device is not unplugged. v2: Add condition of drm_dev_enter() to deleted unmaps in patch "drm/amdgpu: Unmap all MMIO mappings" Signed-off-by:Leslie Shi <Yuliang.Shi@amd.com> Reviewed-by:
Andrey Grodzovsky <andrey.grodzovsky@amd.com> Signed-off-by:
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Peng Ju Zhou authored
Certain Navy Flounder cards have 2 VCNs, enable it. Signed-off-by:
Peng Ju Zhou <PengJu.Zhou@amd.com> Acked-by:
Guchun Chen <guchun.chen@amd.com> Signed-off-by:
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Mario Limonciello authored
When UBSAN is enabled a case is shown on unplugging the display that this variable hasn't been initialized by `update_dsc_caps`, presumably when the display was unplugged it wasn't copied from the DPCD. Link: https://bugs.launchpad.net/ubuntu/+source/linux/+bug/1956497 Signed-off-by:
Mario Limonciello <mario.limonciello@amd.com> Acked-by:
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Jiawei Gu authored
Memory of err_data should be cleaned before usage when there're multiple entry in ras ih. Otherwise garbage data from last loop will be used. Signed-off-by:
Jiawei Gu <Jiawei.Gu@amd.com> Reviewed-by:
Tao Zhou <tao.zhou1@amd.com> Signed-off-by:
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- Jan 08, 2022
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Nicholas Kazlauskas authored
[Why] To maintain compatibility with firmware older than 4.0.11. Those firmware may have interrmittent hangs with RDCSPIPE or the PHY, but we shouldn't regress their previous behavior. [How] Use the new path if firmware is development or 4.0.11 or newer. Use the legacy path otherwise. Fixes: 41f91315 ("drm/amd/display: Query DMCUB for dp alt status") Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Reviewed-by:
Hansen Dsouza <hansen.dsouza@amd.com> Acked-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by:
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by:
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Mikita Lipski authored
[why] We want to know if new crtc state is enabling MPO configuration before enabling it. [how] Detect if both primary and overlay planes are enabled on the same CRTC. Tested-by:
Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Acked-by:
Mikita Lipski <mikita.lipski@amd.com> Signed-off-by:
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Charlene Liu authored
[why] driver missed the check. [how] add the check. add min display clock = 100mhz check based on dccg doc. [note] add SetPhyclkVoltageByFreq as confirmed with smu, but not enabled in this change. Tested-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by:
Charlene Liu <Charlene.Liu@amd.com> Signed-off-by:
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Nicholas Kazlauskas authored
[Why] PSP will suspend and resume DMCUB. Driver should just wait for DMCUB to finish the auto load before continuining instead of placing it into reset, wiping its firmware state and reinitializing. If we don't let DMCUB fully finish initializing for S0ix then some state will be lost and screen corruption can occur due to incorrect address translation. [How] Use dmub_srv callbacks to determine in DMCUB is running and wait for auto-load to complete before continuining. In S0ix DMCUB will be running and DAL fw so initialize will skip. In S3 DMCUB will not be running and we will do a full hardware init. In S3 DMCUB will be running but will not be DAL fw so we will also do a full hardware init. Tested-by:
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Wenjing Liu authored
[why] 1. Current code hard codes link to PHY mapping in dc link level per asic per revision. This is not scalable. In long term the mapping will be obatined from DMUB and store in dc resource. 2. Depending on DCN revision and endpoint type, the definition of dio_output_idx dio_output_type and phy_idx are not consistent. We need to unify the meaning of these hardware indices across different system configuration. [how] 1. Temporarly move the hardcoded mapping to dc_resource level, which should have full awareness of asic specific configuration and add a TODO comment to move the mapping to DMUB. 2. populate dio_output_idx/phy_idx for all configuration, define usb4_enabled bit instead of dio_output_type as an external enum. Tested-by:
Eric Yang <Eric.Yang2@amd.com> Acked-by:
Wenjing Liu <wenjing.liu@amd.com> Signed-off-by:
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Yi-Ling Chen authored
[Why] Depend on res_pool->res_cap->num_timing_generator to query timing gernerator information, it would case underflow at the fused display pipes case. Due to the res_pool->res_cap->num_timing_generator records default timing generator resource built in driver, not the current chip. [How] Some ASICs would be fused display pipes less than the default setting. In dcnxx_resource_construct function, driver would obatin real timing generator count and store it into res_pool->timing_generator_count. Tested-by:
Anthony Koo <Anthony.Koo@amd.com> Acked-by:
Yi-Ling Chen <Yi-Ling.Chen2@amd.com> Signed-off-by:
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Mario Limonciello authored
This makes it clearer which codepaths are in use specifically in one state or the other. Signed-off-by:
Evan Quan <evan.quan@amd.com> Signed-off-by:
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Mario Limonciello authored
This codepath should be running in both s0ix and s3, but only does currently because s3 and s0ix are both set in the s0ix case. Signed-off-by:
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Evan Quan authored
To pair with the workaround which always reset the ASIC in suspend. Otherwise, the reset which relies on BACO will fail. Fixes: daf8de08 ("drm/amdgpu: always reset the asic in suspend (v2)") Signed-off-by:
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James Yao authored
[why] Malicious mailbox event1 fails driver loading on vega10. A dummy event6 prevent driver from taking response from malicious event1 as its own. [how] On vega10, send a mailbox event6 before sending event1. Signed-off-by:
James Yao <yiqing.yao@amd.com> Reviewed-by:
Jingwen Chen <Jingwen.Chen2@amd.com> Signed-off-by:
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yipechai authored
Enable sdma ecc interrupt event can be handled by event_interrupt_wq_v9. Signed-off-by:
yipechai <YiPeng.Chai@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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- Dec 31, 2021
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ssh://gitlab.freedesktop.org/agd5f/linuxDave Airlie authored
amd-drm-next-5.17-2021-12-30: amdgpu: - Suspend/resume fixes - Fence fix - Misc code cleanups - IP discovery fixes - SRIOV fixes - RAS fixes - GMC 8 VRAM detection fix - FRU fixes for Aldebaran - Display fixes amdkfd: - SVM fixes - IP discovery fixes Signed-off-by:
Dave Airlie <airlied@redhat.com> From: Alex Deucher <alexander.deucher@amd.com> Link: https://patchwork.freedesktop.org/patch/msgid/20211230141032.613596-1-alexander.deucher@amd.com
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- Dec 30, 2021
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Alex Deucher authored
Chips with no display hardware should return false for DC support. v2: drop Arcturus and Aldebaran Fixes: f7f12b25 ("drm/amdgpu: default to true in amdgpu_device_asic_has_dc_support") Reviewed-by:
Tareque Md.Hanif <tarequemd.hanif@yahoo.com> Signed-off-by:
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José Expósito authored
The "plane_state" pointer was access before checking if it was NULL. Avoid a possible NULL pointer dereference by accessing the plane address after the check. Addresses-Coverity-ID: 1493892 ("Dereference before null check") Fixes: 3f68c01b ("drm/amd/display: add cyan_skillfish display support") Signed-off-by:José Expósito <jose.exposito89@gmail.com> Reviewed-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
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Alex Deucher authored
If the platform suspend happens to fail and the power rail is not turned off, the GPU will be in an unknown state on resume, so reset the asic so that it will be in a known good state on resume even if the platform suspend failed. v2: handle s0ix Acked-by:
Luben Tuikov <luben.tuikov@amd.com> Acked-by:
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Evan Quan authored
By setting mp1_state as PP_MP1_STATE_UNLOAD, MP1 will do some proper cleanups and put itself into a state ready for PNP. That can workaround some random resuming failure observed on BOCO capable platforms. Signed-off-by:
Lijo Lazar <lijo.lazar@amd.com> Signed-off-by:
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Yizhuo Zhai authored
In function enable_stream_features(), the variable "old_downspread.raw" could be uninitialized if core_link_read_dpcd() fails, however, it is used in the later if statement, and further, core_link_write_dpcd() may write random value, which is potentially unsafe. Fixes: 6016cd9d ("drm/amd/display: add helper for enabling mst stream features") Cc: stable@vger.kernel.org Signed-off-by:
Yizhuo Zhai <yzhai003@ucr.edu> Signed-off-by:
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Alex Deucher authored
It's not only supported by HG/PX laptops. It's supported by all dGPUs which supports BOCO/BACO functionality (runtime D3). BOCO - Bus Off, Chip Off. The entire chip is powered off. This is controlled by ACPI. BACO - Bus Active, Chip Off. The chip still shows up on the PCI bus, but the device itself is powered down. v2: fix missed HG/PX reference Reviewed-by: -
Marina Nikolic authored
== Description == Setting values of pm attributes through sysfs should not be allowed in SRIOV mode. These calls will not be processed by FW anyway, but error handling on sysfs level should be improved. == Changes == This patch prohibits performing of all set commands in SRIOV mode on sysfs level. It offers better error handling as calls that are not allowed will not be propagated further. == Test == Writing to any sysfs file in passthrough mode will succeed. Writing to any sysfs file in ONEVF mode will yield error: "calling process does not have sufficient permission to execute a command". Signed-off-by:
Marina Nikolic <Marina.Nikolic@amd.com> Acked-by:
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Tao Zhou authored
Otherwise the RAS error count couldn't be queried from sysfs. Signed-off-by:
Stanley.Yang <Stanley.Yang@amd.com> Signed-off-by:
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Guchun Chen authored
A minor typo. Signed-off-by:
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Wenjing Liu authored
[why] When reboot the link res map should be persisted. So during boot up, driver will look at the map to determine which link should take priority to use certain link res. This is to ensure that link res remains unshuffled after a reboot. Tested-by:
Jun Lei <Jun.Lei@amd.com> Acked-by:
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Wenjing Liu authored
[why] When there are more DP2.0 RXs connected than the number HPO DP link encoders we have, we need to dynamically allocate HPO DP link encoder to the port that needs it. [how] Only allocate HPO DP link encoder when it is needed. Tested-by:
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Wenjing Liu authored
[why] Update all accesses to use hpo dp link encoder through link resource only. Tested-by:
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Wenjing Liu authored
[why] This commit is to populate link res in preparation of the next commit. The next commit will replace all existing code to use link res instead Tested-by:
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Wenjing Liu authored
[why] There will be a series of re-arch changes in Link Resource Management. They are more and more muxable link resource objects and the resource is insufficient for a one to one allocation to all links created. Therefore a link resource sharing logic is required to determine which link should use certain link resource. This commit is the first one in this series that starts by defining a link resource struct, this struct will be available to all interfaces that need to perform link programming sequence. In later commits, we will granduately decouple link resource objects out of dc link. So instead of access a link resource from dc link. Current link's resource can be accessible through pipe_ctx->link_res during commit, or by calling dc_link_get_cur_link_res function with current link passed in after commit. Tested-by:
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Aric Cyr authored
This version brings along the following: - Fixes and improvements in the LTTPR code - Improve z-state - Fix null pointer check - Improve communication with s0i2 - Update multiple-display split policy - Add missing registers Tested-by:
Aric Cyr <aric.cyr@amd.com> Signed-off-by:
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Anthony Koo authored
Tested-by:
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Martin Leung authored
Undo ODM Combine regression causing causing pipe allocation issues. Tested-by:
Martin Leung <Martin.Leung@amd.com> Signed-off-by:
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Wesley Chalmers authored
[WHY] These registers are currently missing from the DCN303 header files Tested-by:
George Shen <George.Shen@amd.com> Acked-by:
Wesley Chalmers <Wesley.Chalmers@amd.com> Signed-off-by:
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Angus Wang authored
[WHY] Current implementation of pipe split policy prevents pipe split with multiple displays connected, which caused the MCLK speed to be stuck at max [HOW] Changed the pipe split policies so that pipe split is allowed for multi-display configurations Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1522 Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1709 Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1655 Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1403 Tested-by:
Angus Wang <angus.wang@amd.com> Signed-off-by:
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Nicholas Kazlauskas authored
[Why] We'll exit optimized power state to do link detection but we won't enter back into the optimized power state. This could potentially block s2idle entry depending on the sequencing, but it also means we're losing some power during the transition period. [How] Hook up the handler like DCN21. It was also missed like the exit_optimized_pwr_state callback. Fixes: 64b1d0e8 ("drm/amd/display: Add DCN3.1 HWSEQ") Tested-by:
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