- Nov 23, 2019
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changzhu authored
It may lose gpuvm invalidate acknowldege state across power-gating off cycle. To avoid this issue in gmc9/gmc10 invalidation, add semaphore acquire before invalidation and semaphore release after invalidation. After adding semaphore acquire before invalidation, the semaphore register become read-only if another process try to acquire semaphore. Then it will not be able to release this semaphore. Then it may cause deadlock problem. If this deadlock problem happens, it needs a semaphore firmware fix. Signed-off-by:
changzhu <Changfeng.Zhu@amd.com> Acked-by:
Huang Rui <ray.huang@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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changzhu authored
SW must acquire/release one of the vm_invalidate_eng*_sem around the invalidation req/ack. Through this way,it can avoid losing invalidate acknowledge state across power-gating off cycle. To use vm_invalidate_eng*_sem, it needs to initialize vm_invalidate_eng*_sem firstly. Signed-off-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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Jack Zhang authored
After rlcg fw 2.1, kmd driver starts to load extra fw for LIST_CNTL,GPM_MEM,SRM_MEM. We needs to skip the three fw because all rlcg related fw have been loaded by host driver. Guest driver would load the three fw fail without this change. Signed-off-by:
Jack Zhang <Jack.Zhang1@amd.com> Acked-by:
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Jack Zhang authored
Temporarily skip ras,dtm,hdcp initialize and terminate for arcturus VF Currently the three features haven't been enabled at SRIOV, it would trigger guest driver load fail with the bare-metal path of the three features. Signed-off-by:
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Xiaojie Yuan authored
This patch fixes 2nd baco reset failure with gfxoff enabled on navi1x. clear state buffer (resides in vram) is corrupted after 1st baco reset, upon gfxoff exit, CPF gets garbage header in CSIB and hangs. Signed-off-by:
Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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Stephen Rothwell authored
Reviewed-by:
Kevin Wang <kevin1.wang@amd.com> Signed-off-by:
Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by:
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Colin Ian King authored
The pointer write_frame is being initialized with a value that is never read and it is being updated later with a new value. The initialization is redundant and can be removed. Addresses-Coverity: ("Unused value") Signed-off-by:Colin Ian King <colin.king@canonical.com> Signed-off-by:
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Alex Deucher authored
In the standard _PR3 case, the pci core handles the pci state. The driver only needs to handle it in the legacy ATPX case. This may fix issues with runtime suspend/resume on certain hybrid graphics laptops. Acked-by:
Evan Quan <evan.quan@amd.com> Signed-off-by:
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Yong Zhao authored
In the mqd_diq_sdma buffer, there should be only one HIQ mqd. All DIQs should be allocated somewhere else using the regular way. Signed-off-by:
Yong Zhao <Yong.Zhao@amd.com> Reviewed-by:
Oak Zeng <Oak.Zeng@amd.com> Signed-off-by:
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Yong Zhao authored
It is the same as KFD_MQD_TYPE_CP, so delete it. As a result, we will have one less mqd mananger per device. Signed-off-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
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Jay Cornwall authored
Signed-off-by:
Jay Cornwall <jay.cornwall@amd.com> Acked-by:
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Dennis Li authored
Get mmhub error counter by accessing EDC_CNT registers. v2: Add mmhub_v9_4_ prefix for local static variable and function Signed-off-by:
Dennis Li <dennis.li@amd.com> Reviewed-by:
Tao Zhou <tao.zhou1@amd.com> Signed-off-by:
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Dennis Li authored
Add codes to print the detail EDC info for the subblock of mmhub v2: Move the EDC_CNT registers' defintion from mmhub_9_4 header files to mmhub_1_0 ones. Add mmhub_v1_0_ prefix for the local static variable and function. v3: squash in DC fix Signed-off-by:
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Dennis Li authored
The struct soc15_ras_field_entry will be reused by other IPs, such as mmhub and gc v2: rename ras_subblock_regs to gc_ras_fields_vg20, because the future asic maybe have a different table. Signed-off-by:
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Xiaojie Yuan authored
Fixes: 0bb419c7 ("drm/amdgpu/gfx10: fix mqd backup/restore for gfx rings (v2)") Signed-off-by:
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Xiaojie Yuan authored
50us is not enough to wait for cp ready after gpu reset on some navi asics. Signed-off-by:
Jack Xiao <Jack.Xiao@amd.com> Acked-by:
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Alex Sierra authored
Only for the debugger use case. [why] Avoid endless translation retries, after an invalid address access has been issued to the GPU. Instead, the trap handler is forced to enter by generating a no-retry-fault. A s_trap instruction is inserted in the debugger case to let the wave to enter trap handler to save context. [how] Intentionally using an invalid flag combination (F and P set at the same time) to trigger a no-retry-fault, after a retry-fault happens. This is only valid under compute context. Signed-off-by:
Alex Sierra <alex.sierra@amd.com> Reviewed-by:
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Alex Sierra authored
Flag added to indicate if the amdgpu vm context is used for compute or graphics. Signed-off-by:
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- Nov 20, 2019
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Alex Deucher authored
BACO - Bus Active, Chip Off Everything is in place now. Not enabled by default yet. You still have to specify runpm=1. Reviewed-by:
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Alex Deucher authored
Originally we only supported runtime pm on PX/HG laptops so vga_switcheroo and runtime pm are sort of entangled. Attempt to logically separate them. Reviewed-by:
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Alex Deucher authored
BACO - Bus Active, Chip Off BOCO - Bus Off, Chip Off We originally only supported runtime pm on PX/HG laptops so most of the runtime pm code looks for this. Add a new flag to check for runtime pm enablement and use this rather than checking for PX/HG. Reviewed-by:
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Alex Deucher authored
BACO - Bus Active, Chip Off This adds the necessary support to the runtime suspend and resume functions to handle boards that support baco. Reviewed-by:
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Alex Deucher authored
BACO - Bus Active, Chip Off Will be used for runtime pm. Entry will enter the BACO state (chip off). Exit will exit the BACO state (chip on). Reviewed-by:
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Alex Deucher authored
BACO - Bus Active, Chip Off So we can use it for power savings rather than just reset. Reviewed-by:
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Alex Deucher authored
BACO - Bus Active, Chip Off BOCO - Bus Off, Chip Off We will take slightly different paths for boco and baco. v2: fold together two consecutive if clauses Reviewed-by: Evan Quan <evan.quan@amd.com> (v1) Signed-off-by: -
Alex Deucher authored
BACO - Bus Active, Chip Off BOCO - Bus Off, Chip Off To better match what we are checking for and to align with amdgpu_device_supports_baco. BOCO is used on PowerXpress/Hybrid Graphics systems and BACO is used on desktop dGPU boards. v2: fix typo in documentation Reviewed-by:
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Alex Deucher authored
BACO - Bus Active, Chip Off To check if a device supports BACO or not. This will be used in determining when to enable runtime pm. Reviewed-by:
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Alex Deucher authored
BACO - Bus Active, Chip Off Check the BACO capabilities from the powerplay table. Reviewed-by:
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Alex Deucher authored
BACO - Bus Active, Chip Off Check the BACO capabilities from the powerplay table. Reviewed-by:
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Alex Deucher authored
BACO - Bus Active, Chip Off Check the BACO capabilities from the powerplay table. Reviewed-by:
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Alex Deucher authored
BACO - Bus Active, Chip Off Not supported. Reviewed-by:
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Alex Deucher authored
BACO - Bus Active, Chip Off Check the BACO capabilities from the powerplay table. v2: drop unrelated struct cleanup Reviewed-by: Evan Quan <evan.quan@amd.com> (v1) Signed-off-by: -
Alex Deucher authored
BACO - Bus Active, Chip Off Used to check whether the device supports BACO. This will be used to enable runtime pm on devices which support BACO. Reviewed-by:
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changzhu authored
To get the value of gpu_busy_percent, it needs to realize get_current_activity_percent and get_metrics_table. The framework of renoir smu is different from old ones like raven. It needs to realize get_current_activity_percent and get_metrics_table in renoir_ppt.c like navi10. v2: remove unused variable (Alex) Signed-off-by:
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Hawking Zhang authored
ras_controller_irq and athub_err_event_irq are only registered when PCIE_BIF ras is marked as supported. as the result, the driver also just need pull the int status in such case. Signed-off-by:
John Clements <john.clements@amd.com> Signed-off-by:
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Hawking Zhang authored
Drop all the IP specific cmd_submit callback function and use the common helper instead Signed-off-by:
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Hawking Zhang authored
Except for ring wptr update, the psp ring cmd submission function shouldn't be IP specific one. Create a common helper function to be shared for all the ASICs. Signed-off-by:
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Hawking Zhang authored
The ring write pointer regsiter update is the only part that is IP specific ones in psp_cmd_submit function. Add two callbacks for wptr read/write so that we unify the psp_cmd_submit function for all the ASICs. Signed-off-by:
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Evan Quan authored
This can fix the compile errors below: drivers/gpu/drm/amd/amdgpu/../powerplay/smu_v11_0.c: In function ‘smu_v11_0_baco_set_state’: drivers/gpu/drm/amd/amdgpu/../powerplay/smu_v11_0.c:1674:27: error: implicit declaration of function ‘amdgpu_ras_get_context’ [-Werror=implicit-function-declaration] struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); ^ drivers/gpu/drm/amd/amdgpu/../powerplay/smu_v11_0.c:1674:27: warning: initialization makes pointer from integer without a cast [-Wint-conversion] drivers/gpu/drm/amd/amdgpu/../powerplay/smu_v11_0.c:1692:19: error: dereferencing pointer to incomplete type ‘struct amdgpu_ras’ if (!ras || !ras->supported) { Signed-off-by: -
Evan Quan authored
Enable baco reset support on Arcturus. Signed-off-by:
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