- Oct 22, 2020
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John Clements authored
This reverts commit 265c280a . Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
John Clements <john.clements@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Kenneth Feng authored
fix the wrong fan speed in fan1_input when the fan control mode is manual. the fan speed value is not correct when we set manual mode to fan1_enalbe - 1. since the fan speed in the metrics table always reflects the real fan speed,we can fetch the fan speed for both auto and manual mode. Signed-off-by:
Kenneth Feng <kenneth.feng@amd.com> Reviewed-by:
Likun Gao <Likun.Gao@amd.com> Signed-off-by:
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Bas Nieuwenhuizen authored
As far a I can tell uses a variant of DCN3xx which uses num_pkrs. If we do not initialize the variable we will set the register field to ilog2(0) = -1, though the mask will reduce that to 7. Pretty sure 7 is not the value we want here. Signed-off-by:
Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Reviewed-by:
Marek Olšák <marek.olsak@amd.com> Reviewed-and-Tested-by:
Huang Rui <ray.huang@amd.com> Signed-off-by:
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Likun Gao authored
Update driver if file for sienna cichlid. Signed-off-by:
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Likun Gao authored
Fix the function used for sienna cichlid to get correct PCIE information by pp_dpm_pcie. Signed-off-by:
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Alex Deucher authored
Sienna Cichlid and newer have a hw fix so no longer require the workaround. Reviewed-by:
Christian König <christian.koenig@amd.com> Reviewed-by:
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Chengming Gui authored
set noretry default value to 1 for sienna_cichlid/navy_founder/dimgrey_cavefish. Signed-off-by:
Chengming Gui <Jack.Gui@amd.com> Reviewed-by:
Guchun Chen <guchun.chen@amd.com> Signed-off-by:
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Boyuan Zhang authored
Enable VCN 3.0 PG and CG for Vangogh by setting up flags. Signed-off-by:
Boyuan Zhang <boyuan.zhang@amd.com> Reviewed-by:
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Jay Cornwall authored
0 causes instruction fetch stall at cache line boundary under some conditions on Navi10. A non-zero prefetch is the preferred default in any case. Fixes soft hang in Luxmark. Signed-off-by:
Jay Cornwall <jay.cornwall@amd.com> Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
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Kevin Wang authored
1. when smc feature bit isn't mapped, the feature state isn't showed on sysfs node of pp_features. 2. add pp_features table title Signed-off-by:
Kevin Wang <kevin1.wang@amd.com> Reviewed-by:
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Dennis Li authored
because i2c is unstable in GPU reset, driver need protect eeprom update from GPU reset, to not miss any bad page record. Signed-off-by:
Dennis Li <Dennis.Li@amd.com> Reviewed-by:
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- Oct 17, 2020
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Alex Deucher authored
Add a helper so we can set per asic default values. Also, the module parameter is currently clamped to 8, but clamp it per asic just in case some asics have different limits in the future. Enable the option on gfx6,7 as well for consistency. Acked-by:
Nirmoy Das <nirmoy.das@amd.com> Reviewed-by:
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Andrey Grodzovsky authored
psp sysfs not cleaned up on driver unload for sienna_cichlid Fixes: ce87c98d ("drm/amdgpu: Include sienna_cichlid in USBC PD FW support.") Signed-off-by:
Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by:
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Bhawanpreet Lakha authored
Some setups will fail to build. So copy dcn301 makefile setup which is known to work Signed-off-by:
Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by:
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Bhawanpreet Lakha authored
Signed-off-by:
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Andrey Grodzovsky authored
On connector destruction call drm_dp_mst_topology_mgr_destroy to release resources allocated in drm_dp_mst_topology_mgr_init. Do it only if MST manager was initilized before otherwsie a crash is seen on driver unload/device unplug. Reviewed-by:
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by:
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Andrey Grodzovsky authored
This fixes regression on device unplug and/or driver unload. [ 65.681501 < 0.000004>] BUG: kernel NULL pointer dereference, address: 0000000000000008 [ 65.681504 < 0.000003>] #PF: supervisor write access in kernel mode [ 65.681506 < 0.000002>] #PF: error_code(0x0002) - not-present page [ 65.681507 < 0.000001>] PGD 7c9437067 P4D 7c9437067 PUD 7c9db7067 PMD 0 [ 65.681511 < 0.000004>] Oops: 0002 [#1] SMP NOPTI [ 65.681512 < 0.000001>] CPU: 8 PID: 127 Comm: kworker/8:1 Tainted: G W O 5.9.0-rc2-dev+ #59 [ 65.681514 < 0.000002>] Hardware name: System manufacturer System Product Name/PRIME X470-PRO, BIOS 4406 02/28/2019 [ 65.681525 < 0.000011>] Workqueue: events drm_connector_free_work_fn [drm] [ 65.681535 < 0.000010>] RIP: 0010:drm_atomic_private_obj_fini+0x11/0x60 [drm] [ 65.681537 < 0.000002>] Code: de 4c 89 e7 e8 70 f2 ba f8 48 8d 65 d8 5b 41 5c 41 5d 41 5e 41 5f 5d c3 90 0f 1f 44 00 00 48 8b 47 08 48 8b 17 55 48 89 e5 53 <48> 89 42 08 48 89 10 48 b8 00 01 00 00 00 00 ad de 48 89 fb 48 89 [ 65.681541 < 0.000004>] RSP: 0018:ffffa5fa805efdd8 EFLAGS: 00010246 [ 65.681542 < 0.000001>] RAX: 0000000000000000 RBX: ffff9a4b094654d8 RCX: 0000000000000000 [ 65.681544 < 0.000002>] RDX: 0000000000000000 RSI: ffffffffba197bc2 RDI: ffff9a4b094654d8 [ 65.681545 < 0.000001>] RBP: ffffa5fa805efde0 R08: ffffffffba197b82 R09: 0000000000000040 [ 65.681547 < 0.000002>] R10: ffffa5fa805efdc8 R11: 000000000000007f R12: ffff9a4b09465888 [ 65.681549 < 0.000002>] R13: ffff9a4b36f20010 R14: ffff9a4b36f20290 R15: ffff9a4b3a692840 [ 65.681551 < 0.000002>] FS: 0000000000000000(0000) GS:ffff9a4b3ea00000(0000) knlGS:0000000000000000 [ 65.681553 < 0.000002>] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 65.681554 < 0.000001>] CR2: 0000000000000008 CR3: 00000007c9c82000 CR4: 00000000003506e0 [ 65.681556 < 0.000002>] Call Trace: [ 65.681561 < 0.000005>] drm_dp_mst_topology_mgr_destroy+0xc4/0xe0 [drm_kms_helper] [ 65.681612 < 0.000051>] amdgpu_dm_connector_destroy+0x3d/0x110 [amdgpu] [ 65.681622 < 0.000010>] drm_connector_free_work_fn+0x78/0x90 [drm] [ 65.681624 < 0.000002>] process_one_work+0x164/0x410 [ 65.681626 < 0.000002>] worker_thread+0x4d/0x450 [ 65.681628 < 0.000002>] ? rescuer_thread+0x390/0x390 [ 65.681630 < 0.000002>] kthread+0x10a/0x140 [ 65.681632 < 0.000002>] ? kthread_unpark+0x70/0x70 [ 65.681634 < 0.000002>] ret_from_fork+0x22/0x30 This reverts commit 1545fbf9 . Signed-off-by:
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Jiansong Chen authored
Drop navy_flounder hardcode of using soft pptable, so that it can use pptable from vbios when available. Signed-off-by:
Jiansong Chen <Jiansong.Chen@amd.com> Reviewed-by:
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Mihir Bhogilal Patel authored
Add a new list in VM for done state i.e. BOs which are invalidated and updated in PTEs. Signed-off-by:
Mihir Bhogilal Patel <Mihir.Patel@amd.com> Reviewed-by:
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Likun Gao authored
Update golden setting for sienna_cichlid. Signed-off-by:
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Kevin Wang authored
it will cause smu sysfs node of "pp_features" show error. Signed-off-by:
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Kevin Wang authored
remove duplicate gfxhub v1.1 function set. put function of gfxhub_v1_1_get_xgmi_info to gfxhub v1_0 function set. Signed-off-by:
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Chengming Gui authored
noretry = 0 cause some dGPU's kfd page fault tests fail, so set noretry to 1 for these special ASICs: vega20/navi10/navi14 v2: merge raven and default case due to the same setting v3: remove ARCTURUS Signed-off-by:
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Huang Rui authored
This patch is to enable display IP block for vangogh platforms. Signed-off-by:
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Huang Rui authored
DCN301 needs to use dmub create abm instance instead of dce. [ 1138.854204] BUG: kernel NULL pointer dereference, address: 0000000000000000 [ 1138.854206] #PF: supervisor instruction fetch in kernel mode [ 1138.854207] #PF: error_code(0x0010) - not-present page [ 1138.854208] PGD 0 P4D 0 [ 1138.854212] Oops: 0010 [#1] SMP NOPTI [ 1138.854216] CPU: 6 PID: 1240 Comm: modprobe Tainted: G W OE 5.9.0-rc2-custom #1 [ 1138.854217] Hardware name: AMD Chachani-VN/Chachani-VN, BIOS BAerithA104 10/01/2020 [ 1138.854221] RIP: 0010:0x0 [ 1138.854224] Code: Bad RIP value. [ 1138.854226] RSP: 0018:ffffc90001c4f638 EFLAGS: 00010286 [ 1138.854228] RAX: 0000000000000000 RBX: ffff88804f2b2800 RCX: ffffc90001c4f740 [ 1138.854229] RDX: 00000000000000e8 RSI: ffffc90001c4f640 RDI: ffff88805816f300 [ 1138.854230] RBP: ffffc90001c4f850 R08: ffffc90001c4f644 R09: ffffc90001c4f654 [ 1138.854231] R10: ffffc90001c4f72c R11: ffffc90001c4f740 R12: ffffc90001c4f640 [ 1138.854232] R13: ffffc90001c4f728 R14: 0000000000000000 R15: ffff888007296381 [ 1138.854235] FS: 00007f5f44d84540(0000) GS:ffff88805e380000(0000) knlGS:0000000000000000 [ 1138.854236] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 1138.854237] CR2: ffffffffffffffd6 CR3: 00000000194f4000 CR4: 0000000000050ee0 [ 1138.854239] Call Trace: [ 1138.854447] dmub_init_abm_config+0x220/0x267 [amdgpu] [ 1138.854654] dm_late_init+0x197/0x1ad [amdgpu] [ 1138.854846] ? dm_late_init+0x197/0x1ad [amdgpu] [ 1138.854999] amdgpu_device_ip_late_init+0x6f/0x21b [amdgpu] [ 1138.855148] amdgpu_device_init+0x1b7f/0x1cfb [amdgpu] [ 1138.855293] amdgpu_driver_load_kms+0x2c/0x26e [amdgpu] [ 1138.855437] amdgpu_pci_probe+0x1c7/0x249 [amdgpu] [ 1138.920489] local_pci_probe+0x48/0x80 [ 1138.920492] pci_device_probe+0x10f/0x1c0 Signed-off-by:
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Yifan Zhang authored
S/G (scatter/gather) display support for display buffers in system memory. Signed-off-by:
Yifan Zhang <yifan1.zhang@amd.com> Reviewed-by:
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Yifan Zhang authored
[why] display S/G mode fails in Renoir [how] Setup system context in dm init. Signed-off-by:
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- Oct 16, 2020
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Mihir Bhogilal Patel authored
Create new debugfs entry to print memory info using VM buffer objects. V2: Added Common function for printing BO info. Dump more VM lists for evicted, moved, relocated, invalidated. Removed dumping VM mapped BOs. V3: Fixed coding style comments, renamed print API and variables. V4: Fixed coding style comments. Signed-off-by: -
Evan Quan authored
Current code wrongly treat all cases as job == NULL. Signed-off-by:
Evan Quan <evan.quan@amd.com> Reviewed-and-tested-by:
Jane Jian <Jane.Jian@amd.com> Signed-off-by:
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Likun Gao authored
Support to load RLC iram and dram ucode when RLC firmware struct use v2.2 Signed-off-by:
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Likun Gao authored
Add function for sienna_cichlid to force PBB workload mode to zero by checking whether there have SE been harvested. Signed-off-by:
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Jiansong Chen authored
This reverts commit 39ad0824 . TDR issue has been resovled by pmfw update. Signed-off-by:
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Evan Quan authored
Disable/enable the GPO feature on UMD pstate entering/exiting. Signed-off-by:
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Evan Quan authored
Fulfill Navi gfx and pcie settings on umd pstate switching. V2: temporarily skip the pcie ASPM setting considering the ASPM function is not fully enabled yet Signed-off-by: -
Evan Quan authored
Enable Navi1X MGCG perfmon setting. Signed-off-by:
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Evan Quan authored
Support NAVI10 ASPM setting. Signed-off-by:
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Evan Quan authored
For entering UMD stable Pstate, the operations to enter rlc_safe mode, disable mgcg_perfmon and disable PCIE aspm are needed. And the opposite operations should be performed on UMD stable Pstate exiting. V2: take those ASICs(CI/SI/VI) which may not support this into consideration Signed-off-by: -
Evan Quan authored
Populate current link speed, width and clock domain frequency. Signed-off-by:
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Evan Quan authored
As for other clock domains. Signed-off-by:
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Huang Rui authored
This patch fixes the gfx hang while use firmware direct loading mode. Signed-off-by:
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