1. Oct 05, 2020
  2. Oct 02, 2020
  3. Oct 01, 2020
    • Thomas Petazzoni's avatar
      serial: max310x: rework RX interrupt handling · fce3c5c1
      Thomas Petazzoni authored
      
      
      Currently, the RX interrupt logic uses the RXEMPTY interrupt, with the
      RXEMPTYINV bit set, which means we get an RX interrupt as soon as the
      RX FIFO is non-empty.
      
      However, with the MAX310X having a FIFO of 128 bytes, this makes very
      poor use of the FIFO: we trigger an interrupt as soon as the RX FIFO
      has one byte, which means a lot of interrupts, each only collecting a
      few bytes from the FIFO, causing a significant CPU load.
      
      Instead this commit relies on two other RX interrupt events:
      
       - MAX310X_IRQ_RXFIFO_BIT, which triggers when the RX FIFO has reached
         a certain threshold, which we define to be half of the FIFO
         size. This ensure we get an interrupt before the RX FIFO fills up.
      
       - MAX310X_LSR_RXTO_BIT, which triggers when the RX FIFO has received
         some bytes, and then no more bytes are received for a certain
         time. Arbitrarily, this time is defined to the time is takes to
         receive 4 characters.
      
      On a Microchip SAMA5D3 platform that is receiving 20 bytes every 16ms
      over one MAX310X UART, this patch has allowed to reduce the CPU
      consumption of the interrupt handler thread from ~25% to 6-7%.
      
      Signed-off-by: default avatarThomas Petazzoni <thomas.petazzoni@bootlin.com>
      Link: https://lore.kernel.org/r/20201001074415.349739-1-thomas.petazzoni@bootlin.com
      
      
      Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
      fce3c5c1
  4. Sep 30, 2020
  5. Sep 29, 2020
  6. Sep 27, 2020
  7. Sep 22, 2020
  8. Sep 21, 2020