- Jul 17, 2022
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Jernej Skrabec authored
During decoding setup stage for complex codecs like HEVC driver can detect inconsistent values in controls or some other task, like allocating memory, can fail. Currently setup stage has no way of signalling error. Change return type of setup callback to int and if returned value is not zero, skip decoding and finish job immediately with error flag. While currently there is only one place when setup can fail, it's expected that there will be more such cases in the future, when HEVC decoding is improved. Signed-off-by:
Jernej Skrabec <jernej.skrabec@gmail.com> Reviewed-by:
Ezequiel Garcia <ezequiel@vanguardiasur.com.ar> Signed-off-by:
Hans Verkuil <hverkuil-cisco@xs4all.nl> Signed-off-by:
Mauro Carvalho Chehab <mchehab@kernel.org>
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Jernej Skrabec authored
Currently error messages when control creation fails are very sparse. Granted, user should never observe them. However, developer working on codecs can. In such cases additional information like which control creation failed and error number are very useful. Expand error messages with additional info. Signed-off-by:
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Jernej Skrabec authored
Now that we know real purpose of "not low delay" flag, logic for applying this flag should be fixed too. According to vendor and reference implementation, low delay is signaled when POC of current frame is lower than POC of at least one reference of a slice. Implement mentioned logic and invert it to conform to flag meaning. Also don't apply flag for I frames. They don't have any reference. This fixes decoding of 3 reference bitstreams. Fixes: 86caab29 ("media: cedrus: Add HEVC/H.265 decoding support") Signed-off-by:
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Jernej Skrabec authored
Bit 21 in register 0x24 (slice header info 1) actually represents negated version of low delay flag. This can be seen in vendor Cedar library source code. While this flag is not part of the standard, it can be found in reference HEVC implementation. Fix macro name and change it to flag. Fixes: 86caab29 ("media: cedrus: Add HEVC/H.265 decoding support") Signed-off-by:
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Jernej Skrabec authored
Now that infrastructure for 10-bit decoding exists, enable it for Allwinner H6. Tested-by:
Benjamin Gaignard <benjamin.gaignard@collabora.com> Signed-off-by:
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Jernej Skrabec authored
Now that we have proper infrastructure for postprocessing 10-bit formats, store VP9 bit depth in context. Reviewed-by:
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Jernej Skrabec authored
Currently chroma offset calculation assumes only 1 byte per luma, with no consideration for stride. Take necessary information from destination pixel format which makes calculation completely universal. Reviewed-by:
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Jernej Skrabec authored
Some postproc legacy registers were set in VP9 code. Move them to postproc and fix their value. Reviewed-by:
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Jernej Skrabec authored
When allocating aux buffers for postprocessing, it's assumed that base buffer size is the same as that of output. Coincidentally, that's true most of the time, but not always. 10-bit source also needs aux buffer size which is appropriate for 10-bit native format, even if the output format is 8-bit. Similarly, mv sizes and other extra buffer size also depends on source width/height, not destination. Reviewed-by:
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Jernej Skrabec authored
In preparation for supporting 10-bit formats, add mechanism which will filter formats based on pixel depth. Hantro G2 supports only one decoding format natively and that is based on bit depth of current video frame. Additionally, it makes no sense to upconvert bitness, so filter those out too. Reviewed-by:
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Ezequiel Garcia authored
Add P010 tiled format [rebased, updated pixel format name and added description] Tested-by:
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- Jul 16, 2022
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Michael Grzeschik authored
The goto statement in uvc_v4l2_try_format can simply be replaced by an direct return. There is no further user of the label, so remove it. Signed-off-by:
Michael Grzeschik <m.grzeschik@pengutronix.de> Reviewed-by:
Paul Elder <paul.elder@ideasonboard.com> Signed-off-by:
Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by:
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Ricardo Ribalda authored
The device does not implement the power line control correctly. Add a corresponding control mapping override. Bus 001 Device 003: ID 5986:1172 Acer, Inc EasyCamera Device Descriptor: bLength 18 bDescriptorType 1 bcdUSB 2.00 bDeviceClass 239 Miscellaneous Device bDeviceSubClass 2 bDeviceProtocol 1 Interface Association bMaxPacketSize0 64 idVendor 0x5986 Acer, Inc idProduct 0x1172 bcdDevice 56.04 iManufacturer 3 Bison iProduct 1 EasyCamera iSerial 2 bNumConfigurations 1 Signed-off-by:
Ricardo Ribalda <ribalda@chromium.org> Signed-off-by:
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Ricardo Ribalda authored
Two more cameras do not implement the power line control correctly. Add a corresponding control mapping override. Bus 001 Device 003: ID 0408:4034 Quanta Computer, Inc. ACER HD User Facing Device Descriptor: bLength 18 bDescriptorType 1 bcdUSB 2.01 bDeviceClass 239 Miscellaneous Device bDeviceSubClass 2 bDeviceProtocol 1 Interface Association bMaxPacketSize0 64 idVendor 0x0408 Quanta Computer, Inc. idProduct 0x4034 bcdDevice 0.01 iManufacturer 1 Quanta iProduct 2 ACER HD User Facing iSerial 3 01.00.00 bNumConfigurations 1 Bus 001 Device 003: ID 0408:4030 Quanta Computer, Inc. HD User Facing Device Descriptor: bLength 18 bDescriptorType 1 bcdUSB 2.01 bDeviceClass 239 Miscellaneous Device bDeviceSubClass 2 bDeviceProtocol 1 Interface Association bMaxPacketSize0 64 idVendor 0x0408 Quanta Computer, Inc. idProduct 0x4030 bcdDevice 0.02 iManufacturer 1 Quanta iProduct 2 HD User Facing iSerial 3 01.00.00 bNumConfigurations 1 Signed-off-by:
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Ricardo Ribalda authored
Another Chicony camera device does not implement the power line control correctly. Add a corresponding control mapping override. Bus 001 Device 003: ID 04f2:b5eb Chicony Electronics Co., Ltd EasyCamera Device Descriptor: bLength 18 bDescriptorType 1 bcdUSB 2.00 bDeviceClass 239 Miscellaneous Device bDeviceSubClass 2 bDeviceProtocol 1 Interface Association bMaxPacketSize0 64 idVendor 0x04f2 Chicony Electronics Co., Ltd idProduct 0xb5eb bcdDevice 90.45 iManufacturer 3 Chicony Electronics Co.,Ltd. iProduct 1 EasyCamera iSerial 2 0001 bNumConfigurations 1 Signed-off-by:
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Ricardo Ribalda authored
Two different Easycamera devices do not implement the power line control correctly. Add a corresponding control mapping override. Bus 001 Device 003: ID 04f2:b6ba Chicony Electronics Co., Ltd EasyCamera Device Descriptor: bLength 18 bDescriptorType 1 bcdUSB 2.00 bDeviceClass 239 Miscellaneous Device bDeviceSubClass 2 bDeviceProtocol 1 Interface Association bMaxPacketSize0 64 idVendor 0x04f2 Chicony Electronics Co., Ltd idProduct 0xb6ba bcdDevice 10.70 iManufacturer 3 Chicony Electronics Co.,Ltd. iProduct 1 EasyCamera iSerial 2 0001 bNumConfigurations 1 Bus 001 Device 003: ID 04f2:b746 Chicony Electronics Co., Ltd EasyCamera Device Descriptor: bLength 18 bDescriptorType 1 bcdUSB 2.00 bDeviceClass 239 Miscellaneous Device bDeviceSubClass 2 bDeviceProtocol 1 Interface Association bMaxPacketSize0 64 idVendor 0x04f2 Chicony Electronics Co., Ltd idProduct 0xb746 bcdDevice 97.57 iManufacturer 3 Chicony Electronics Co.,Ltd. iProduct 1 EasyCamera iSerial 2 0001 bNumConfigurations 1 Signed-off-by:
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Ricardo Ribalda authored
The device does not implement the power line control correctly. Add a corresponding control mapping override. Bus 001 Device 003: ID 0408:3090 Quanta Computer, Inc. USB2.0 HD UVC WebCam Device Descriptor: bLength 18 bDescriptorType 1 bcdUSB 2.00 bDeviceClass 239 Miscellaneous Device bDeviceSubClass 2 bDeviceProtocol 1 Interface Association bMaxPacketSize0 64 idVendor 0x0408 Quanta Computer, Inc. idProduct 0x3090 bcdDevice 0.04 iManufacturer 3 Quanta iProduct 1 USB2.0 HD UVC WebCam iSerial 2 0x0001 bNumConfigurations 1 Signed-off-by:
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Ricardo Ribalda authored
Some devices do not implement all their controls in a way that complies with the UVC specification. This is for instance the case for several devices that do not support the disabled mode for the power line frequency control. Add a mechanism to allow per-device control mapping overrides to avoid errors when accessing non-compliant controls. Signed-off-by:
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Ricardo Ribalda authored
UVC 1.5 class defines 4 values for this control on: 4.2.2.3.6 Power Line Frequency Control Add the missing value when the UVC version is 1.5. Signed-off-by:
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Laurent Pinchart authored
The link to the web page that explains continued fractions is broken. Replace it with a link to the corresponding Wikipedia page. Reported-by:
Kieran Bingham <kieran.bingham+renesas@ideasonboard.com> Signed-off-by:
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Laurent Pinchart authored
The uvcvideo driver historically uses the /* Comment * style */ for multi-line block comments, which is frowned upon. Patches for the driver are required to use the more standard /* * Comment * style */ style. This result in inconsistencies. Fix it by converting all remaining instances of the old style. Signed-off-by:
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Laurent Pinchart authored
The CSIS CSI-2 receiver in the i.MX8MP seems to be identical to the version present in the i.MX8MM. Add a device-specific compatible string, with a fallback to the i.MX8MM compatible. Signed-off-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by:
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Laurent Pinchart authored
The CSIS is connected to its sink through an SoC-specific gasket that needs to be configured. Depending on the platform, the gasket configuration requires knowing the CSI-2 DT. To provide the needed information, implement the .get_frame_desc() operation. Signed-off-by:
Rui Miguel Silva <rmfrfs@gmail.com> Signed-off-by:
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Laurent Pinchart authored
Register at offset 0x00 isn't documented, but the NXP BSP imx8-mipi-csi2-sam driver defines it as a version register. Tests on i.MX7D and i.MX8MP have confirmed this, with values matching the version of the IP core specified in the respective reference manuals. This commit doesn't make use of the version register at runtime as the compatible strings are enough to identify the IP core version. Nonetheless, capturing the information in register definitions that don't affect the code negatively is useful for future development. Signed-off-by:
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Laurent Pinchart authored
Endpoint matching is preferred over device matching with the async notifier framework. Set the fwnode in the v4l2_subdev for the CSIS to the endpoint connected to the next device. Signed-off-by:
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Benjamin Gaignard authored
HEVC uAPI is used by 2 mainline drivers (Hantro, Cedrus) and at least 2 out-of-tree drivers (rkvdec, RPi). The uAPI has been reviewed so it is time to make it 'public' by un-staging it. Signed-off-by:
Nicolas Dufresne <nicolas.dufresne@collabora.com> Tested-by:
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Benjamin Gaignard authored
'F.7.3.6.1 General slice segment header syntax' section of HEVC specification describes that a slice header always end aligned on byte boundary, therefore we only need to provide the data offset in bytes. Signed-off-by:
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Benjamin Gaignard authored
Fix padding where needed to remove holes Signed-off-by:
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Benjamin Gaignard authored
The number of bits to skip in the slice header can be computed in the driver by using sps, pps and decode_params information. This makes it possible to remove Hantro dedicated control. Signed-off-by:
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Benjamin Gaignard authored
Simply print the type of the control. Signed-off-by:
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Benjamin Gaignard authored
Move the HEVC stateless controls types out of staging, and re-number them. Signed-off-by:
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Benjamin Gaignard authored
Move HEVC pixel format since we are ready to stabilize the uAPI Signed-off-by:
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Benjamin Gaignard authored
The number of 'entry point offset' can be very variable. Instead of using a large static array define a v4l2 dynamic array of U32 (V4L2_CTRL_TYPE_U32). The number of entry point offsets is reported by the elems field and in struct v4l2_ctrl_hevc_slice_params.num_entry_point_offsets field. Signed-off-by:
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- Jul 15, 2022
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Benjamin Gaignard authored
Make explicit that V4L2_CID_STATELESS_HEVC_SLICE_PARAMS control is a dynamic array control type. Some drivers may be able to receive multiple slices in one control to improve decoding performance. Signed-off-by:
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Benjamin Gaignard authored
Add kernel-doc documentation for all the HEVC structures. Signed-off-by:
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Benjamin Gaignard authored
The possible values for the field_pic field in the v4l2_hevc_dpb_entry structure are defined in the table D.2 in HEVC specification section D.3.3. Add flags and documentation for each of them. Signed-off-by:
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Benjamin Gaignard authored
The HEVC specification describes the following: "PicOrderCntVal is derived as follows: PicOrderCntVal = PicOrderCntMsb + slice_pic_order_cnt_lsb The value of PicOrderCntVal shall be in the range of −2^31 to 2^31 − 1, inclusive." To match with these definitions change __u16 pic_order_cnt[2] into __s32 pic_order_cnt_val. Change v4l2_ctrl_hevc_slice_params->slice_pic_order_cnt to __s32 too. Signed-off-by:
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Benjamin Gaignard authored
Change HEVC stateless controls names to V4L2_CID_STATELESS_HEVC instead of V4L2_CID_MPEG_VIDEO_HEVC be coherent with v4l2 naming convention. Signed-off-by:
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Benjamin Gaignard authored
Complete the HEVC controls with missing fields from H.265 specifications. Even if these fields aren't used by the current mainlined drivers they will be required for (at least) the rkvdec driver. Signed-off-by:
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Hans Verkuil authored
Add a dynamic array test control to help test support for this feature. Acked-by:
Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by:
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