- May 14, 2011
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Eric Anholt authored
They have been moved from the ringbuffer groups to their own group it looks like. Fixes GPU hangs on gnome startup. Signed-off-by:
Eric Anholt <eric@anholt.net> Reviewed-by:
Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by:
Keith Packard <keithp@keithp.com>
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Eric Anholt authored
The registers are the same as on Sandybridge. Fixes scrambled display in X when it does software drawing to the GTT, and scans the results out as tiled. Signed-off-by:
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Eric Anholt authored
This is once less place to miss a new INTEL_INFO(dev)->gen update now. Signed-off-by:
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Jesse Barnes authored
This helps contain the mess to init_display() instead. Signed-off-by:
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Jesse Barnes authored
This is a little less confusing than relying on the implicit zeroing of the dev_priv. Signed-off-by:
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Jesse Barnes authored
There are several variants, set feature bits appropriately for both mobile and desktop parts. Signed-off-by:
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Jesse Barnes authored
We can treat PantherPoint as CougarPoint as far as display goes. Signed-off-by:
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Jesse Barnes authored
Just use the Sandy Bridge routines. Signed-off-by:
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Jesse Barnes authored
Use Sandy Bridge paths in a few places. Signed-off-by:
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Jesse Barnes authored
Treat Ivy Bridge like previous chips as far as flip submission is concerned. Signed-off-by:
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Jesse Barnes authored
Add new interrupt handling functions for Ivy Bridge. Signed-off-by:
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Jesse Barnes authored
Not fully tested. Signed-off-by:
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Jesse Barnes authored
A0 stepping chips need to use manual training, but the bits have all moved. So fix things up so we can at least train FDI for VGA links. Signed-off-by:
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Jesse Barnes authored
Treat it like Ironlake and Sandy Bridge. Signed-off-by:
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Jesse Barnes authored
Ivy Bridge has a similar split display controller to Sandy Bridge, so use HAS_PCH_SPLIT. And gen7 also has the pipe control instruction, so use HAS_PIPE_CONTROL as well. Signed-off-by:
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Jesse Barnes authored
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Jesse Barnes authored
Note: IS_GEN* are for render related checks. Display and other checks should use IS_MOBILE, IS_$CHIPSET or test for specific features. Signed-off-by:
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Jesse Barnes authored
This makes the Ironlake+ code trivial and generally simplifies things. Signed-off-by:
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Jesse Barnes authored
Set the IRQ handling functions in driver load so they'll just be used directly, rather than branching over most of the code in the chipset functions. Signed-off-by:
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Jesse Barnes authored
Rather than branching in ironlake_pch_enable, add a new train_fdi function to the display function pointer struct and use it instead. Signed-off-by:
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Ben Widawsky authored
Forcewake needs to register itself with drm to use the remove function. The file also should be read only. Signed-off-by:
Ben Widawsky <ben@bwidawsk.net> Signed-off-by:
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- May 11, 2011
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Keith Packard authored
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Ben Widawsky authored
forcewake is controlled by the open and close of the debugfs file. This assures that buggy applications cannot cause the GT to stay on forever. Signed-off-by:
Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by:
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Ben Widawsky authored
The render P-state handling code requires reading from a GT register. This means that FORCEWAKE must be written to, a resource which is shared and should be protected by struct_mutex. Hence we can not manipulate that register from within the interrupt handling and so must delegate the task to a workqueue. Signed-off-by:
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Ben Widawsky authored
Found by the new strict checking for the mutex being held whilst manipulating the forcewake status. Signed-off-by:
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Ben Widawsky authored
Provide a reference count to track the forcewake state of the GPU and give a safe mechanism for userspace to wake the GT. This also potentially saves a UC read if the GT is known to be awake already. The reference count is atomic, but the register access and hardware wake sequence is protected by struct_mutex. Signed-off-by:
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Ben Widawsky authored
Moved the macros around to properly do reads and writes for the given GPU. This is to address special requirements for gen6 (SNB) reads and writes. Registers in the range 0-0x40000 on gen6 platforms require special handling. Instead of relying on the callers to pick the registers correctly, move the logic into the read and write functions. Signed-off-by:
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Chris Wilson authored
If the outputs are active and continuing to access the GATT when we teardown the PTEs, then there is a potential for us to hang the GPU. The hang tends to be a PGTBL_ER with either an invalid host access or an invalid display plane fetch. v2: Reorder IRQ initialisation to defer until after GEM is setup. Reported-by:
Pekka Enberg <penberg@kernel.org> Signed-off-by:
Rick Bramley <richard.bramley@hp.com> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=35635 Reported-and-tested-by:
Zdenek Kabelac <zdenek.kabelac@gmail.com> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=36048 Reviewed-by:
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Chris Wilson authored
Rely on the GPU snooping into the CPU cache for appropriately bound objects on MI_FLUSH. Or perhaps one day we will have a cache-coherent CPU/GPU package... Signed-off-by:
Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by:
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Chris Wilson authored
... to clarify just how we use it inside the driver and remove the confusion of the poorly matching agp_type names. We still need to translate through agp_type for interface into the fake AGP driver. Signed-off-by:
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Ben Widawsky authored
Currently this is only useful for the rc6 stuff. But this would also be useful when I finally get around to the logical context + ppgtt stuff. Signed-off-by:
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Jesse Barnes authored
For debug & testing. Signed-off-by:
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Ben Widawsky authored
There is a race condition between setting PWRCTXA and executing MI_SET_CONTEXT. PWRCTXA must not be set until a valid context has been written (or else the GPU could possible go into rc6, and return to an invalid context). Reported-and-Tested-by:
Gu Rui <chaos.proton@gmail.com> Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=28582 Signed-off-by:
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Ben Widawsky authored
Added a new function which waits for the ringbuffer space to be equal to (total - 8). This is the empty condition of the ringbuffer, and equivalent to head==tail. Also modified two users of this functionality elsewhere in the code. Signed-off-by:
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Ben Widawsky authored
In the failure cases during rc6 initialization, both the power context and render context may get !refcount without holding struct_mutex. However, on rc6 disabling, the lock is held by the caller. Rearranged the locking so that it's safe in both cases. Signed-off-by:
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Eric Anholt authored
They're used in one place, and not providing any descriptive value, with their names just being approximately the conjunction of the struct name and the struct field. This diff was produced with gcc -E, copying the new struct definitions out, moving a couple of the old comments into place in the new structs, and reindenting. Signed-off-by:
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Eric Anholt authored
We used to have these from the product of (pch, non-pch) * (pipe a, pipe b). Now we can just use the nice per-pipe reg macros in the split out crtc_mode_sets. Signed-off-by:
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Eric Anholt authored
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Eric Anholt authored
Ironlake is where the PCH split started. Signed-off-by:
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Eric Anholt authored
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