Skip to content
GitLab
  1. Jun 23, 2013
  3. Jun 21, 2013
    • Heiko Stübner's avatar
      clk: add support for Rockchip gate clocks · 646572c7
      Heiko Stübner authored 
      

This adds basic support for gate-clocks on Rockchip SoCs.
There are 16 gates in each register and use the HIWORD_MASK
mechanism for changing gate settings.

The gate registers form a continuos block which makes the dt node
structure a matter of taste, as either all 160 gates can be put into
one gate clock spanning all registers or they can be divided into
the 10 individual gates containing 16 clocks each.
The code supports both approaches.

Signed-off-by: default avatarHeiko Stuebner <heiko@sntech.de>
Signed-off-by: default avatarMike Turquette <mturquette@linaro.org>
      646572c7
  5. Jun 20, 2013
  7. Jun 19, 2013
    • Paul Walmsley's avatar
      clk: tegra: T114: add DFLL DVCO reset control · 1c472d8e
      Paul Walmsley authored 
      

Add DFLL DVCO reset line control functions to the CAR IP block driver.

The DVCO present in the DFLL IP block has a separate reset line,
exposed via the CAR IP block.  This reset line is asserted upon SoC
reset.  Unless something (such as the DFLL driver) deasserts this
line, the DVCO will not oscillate, although reads and writes to the
DFLL IP block will complete.

Thanks to Aleksandr Frid <afrid@nvidia.com> for identifying this and
saving hours of debugging time.

Signed-off-by: default avatarPaul Walmsley <pwalmsley@nvidia.com>
Cc: Aleksandr Frid <afrid@nvidia.com>
Cc: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: default avatarMike Turquette <mturquette@linaro.org>
      1c472d8e
    • Paul Walmsley's avatar
      clk: tegra: T114: add DFLL source clocks · 9e60121f
      Paul Walmsley authored 
      

Add the input clocks needed by the DFLL IP blocks.  Initialize them to
51MHz (as required by the DFLL GFD) and to use the PLL_P clock source.

This patch is a collaboration with Peter De Schrijver
<pdeschrijver@nvidia.com>.

Thanks to Laxman Dewangan <ldewangan@nvidia.com> for identifying the
requirement to keep the DFLL clocks enabled to resolve PWR_I2C timeout
issues.

Signed-off-by: default avatarPaul Walmsley <pwalmsley@nvidia.com>
Cc: Peter De Schrijver <pdeschrijver@nvidia.com>
Reviewed-by: default avatarAndrew Chew <achew@nvidia.com>
Cc: Matthew Longnecker <mlongnecker@nvidia.com>
Cc: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: default avatarMike Turquette <mturquette@linaro.org>
      9e60121f
    • Paul Walmsley's avatar
      clk: tegra: T114: add FCPU clock shaper programming, needed by the DFLL · 25c9ded6
      Paul Walmsley authored 
      

Add clock functions to initialize, enable, and disable the FCPU clock
shapers, based on the FCPU voltage rail state.  These will be used by
the DFLL clocksource driver code.

This version of the patch contains a fix for a problem noticed by Andrew
Chew <achew@nvidia.com>, where some of the FINETRIM_R bitfields were
incorrectly defined.

Based on code originally written by Aleksandr Frid <afrid@nvidia.com>.

Signed-off-by: default avatarPaul Walmsley <pwalmsley@nvidia.com>
Cc: Andrew Chew <achew@nvidia.com>
Reviewed-by: default avatarAndrew Chew <achew@nvidia.com>
Cc: Matthew Longnecker <mlongnecker@nvidia.com>
Cc: Aleksandr Frid <afrid@nvidia.com>
Signed-off-by: default avatarMike Turquette <mturquette@linaro.org>
      25c9ded6
  9. Jun 16, 2013
  11. Jun 12, 2013
  13. Jun 11, 2013
    • Shawn Guo's avatar
      clk: divider: do not propagate rate change request when unnecessary · 081c9025
      Shawn Guo authored 
      

If the current rate of parent clock is sufficient to provide child a
requested rate with a proper divider setting, the rate change request
should not be propagated.  Instead, changing the divider setting is good
enough to get child clock run at the requested rate.

On an imx6q clock configuration illustrated below,

  ahb --> ipg --> ipg_per
  132M    66M     66M

calling clk_set_rate(ipg_per, 22M) with the current
clk_divider_bestdiv() implementation will result in the rate change up
to ahb level like the following, because of the unnecessary/incorrect
rate change propagation.

  ahb --> ipg --> ipg_per
  66M     22M     22M

Fix the problem by trying to see if the requested rate can be achieved
by simply changing the divider value, and in that case return the
divider immediately from function clk_divider_bestdiv() as the best
one, so that all those unnecessary rate change propagation can be saved.

Reported-by: default avatarAnson Huang <b20788@freescale.com>
Signed-off-by: default avatarShawn Guo <shawn.guo@linaro.org>
Signed-off-by: default avatarMike Turquette <mturquette@linaro.org>
      081c9025
  15. Jun 07, 2013
  17. Jun 05, 2013
  19. Jun 01, 2013
  21. May 31, 2013
  23. May 30, 2013