- May 07, 2013
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Arnd Bergmann authored
This is support for the ARM Chromebook, originally scheduled as a "late" pull request. Since it's already late now, we can combine this into the existing next/dt2 branch. * late/dt: ARM: exynos: dts: cros5250: add EC device ARM: dts: Add sbs-battery for exynos5250-snow ARM: dts: Add i2c-arbitrator bus for exynos5250-snow ARM: dts: Add chip-id controller node on Exynos4/5 SoC ARM: EXYNOS: Create virtual I/O mapping for Chip-ID controller using device tree
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- Apr 29, 2013
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Olof Johansson authored
Merge tag 'late-exynos-v3-for-v3.10' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into late/dt From Kukjin Kim: This allows that device tree enables platform to setup a runtime IO mapping for the chip id * tag 'late-exynos-v3-for-v3.10' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung : ARM: dts: Add chip-id controller node on Exynos4/5 SoC ARM: EXYNOS: Create virtual I/O mapping for Chip-ID controller using device tree Signed-off-by:
Olof Johansson <olof@lixom.net>
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Olof Johansson authored
Add basic EC information to device tree, currently only describing the keyboard and keymap. Reviewed-by:
Doug Anderson <dianders@chromium.org> Acked-by:
Kukjin Kim <kgene.kim@samsung.com> Signed-off-by:
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Doug Anderson authored
Now that we have i2c-arbitrator in place on bus 4 we can add the sbs-battery driver. Future devices will be added onto bus 4 once drivers are in good shape. Signed-off-by:
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Doug Anderson authored
We need to use the i2c-arbitrator to talk to any of the devices on i2c bus 4 on exynos5250-snow so that we don't confuse the embedded controller (EC). Add the i2c-arbitrator to the device tree. As we add future devices (keyboard, sbs, tps65090) we'll add them on top of this. The arbitrated bus is numbered 104 simply as a convenience to make it easier for people poking around to guess that it might have something to do with the physical bus 4. The addition is split between the cros5250-common and the snow device tree file since not all cros5250-class devices use arbitration. Signed-off-by:
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Olof Johansson authored
* exynos/dt: (125 commits) ARM: dts: add PDMA0 changes for exynos5440 ARM: dts: Add cpufreq controller node for Exynos5440 SoC ARM: dts: Fix gmac clock ids due to changes in Exynos5440 ARM: dts: add device tree file for SD5v1 board ARM: dts: update bootargs to boot from sda2 for exynos5440-ssdk5440 ARM: dts: add PMU support in exynos5440 ARM: dts: Add node for GMAC for exynos5440 ARM: dts: list the interrupts generated by pin-controller on Exynos5440 ARM: dts: Add FIMD DT binding Documentation ARM: dts: Add FIMD node and display timing node to exynos4412-origen.dts ARM: dts: Add FIMD node to exynos4 ARM: dts: Add SYSREG block node for S5P/Exynos4 SoC series ARM: dts: Add display timing node to exynos5250-smdk5250.dts ARM: dts: Add FIMD node to exynos5 ARM: dts: Add virtual GIC DT bindings for exynos5440 ARM: dts: Document usb clocks in samsung,exynos4210-ehci/ohci bindings ARM: dts: add usb 2.0 clock references to exynos5250 device tree ARM: dts: Add architected timer nodes for exynos5250 ARM: dts: Declare the gic as a15 compatible for exynos5250 ARM: dts: Add HDMI HPD and regulator node for Arndale board ...
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Olof Johansson authored
* samsung/pinctrl-exynos: ARM: EXYNOS: skip wakeup interrupt registration for exynos5250 if pinctrl is enabled gpio: samsung: skip gpiolib registration if pinctrl support is enabled for exynos5250 pinctrl: exynos: add exynos5250 SoC specific data
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- Apr 27, 2013
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Thomas Abraham authored
Commit 800974ac ("ARM: dts: Add board dts file for ODROID-X") includes a node to describe the board level properties for mshc controller. But the mshc controller node was not added in the Exynos4x12 dtsi file which resulted in the following warning when compiling the dtb files. Warning (reg_format): "reg" property in /mshc@12550000/slot@0 has invalid length (4 bytes) (#address-cells == 2, #size-cells == 1) Warning (avoid_default_addr_size): Relying on default #address-cells value for /mshc@12550000/slot@0 Warning (avoid_default_addr_size): Relying on default #size-cells value for /mshc@12550000/slot@0 Fix this by adding the mshc controller node for Exynos4x12 SoCs. Signed-off-by:
Thomas Abraham <thomas.abraham@linaro.org> Tested-by:
Dongjin Kim <tobetter@gmail.com> Signed-off-by:
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- Apr 26, 2013
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Thomas Abraham authored
Add chip-id controller nodes for Exynos4 and Exynos5 SoCs. Signed-off-by:
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Thomas Abraham authored
On device tree enabled exynos platforms, retrieve the physical base address of the chip-id controller from device tree and create a virtual I/O mapping for the chip-id controller. This helps to remove the chip-id controller entry from the statically defined I/O mapping tables. Signed-off-by:
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- Apr 18, 2013
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Olof Johansson authored
Merge tag 'davinci-for-v3.10/dt-2-v2' of git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci into next/dt2 From Sekhar Nori: v3.10 DT updates for DaVinci This set of patches adds support for PWMs and SPI controller present on DA850 and for SPI flash present on DA850 EVM. * tag 'davinci-for-v3.10/dt-2-v2' of git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci : ARM: davinci: da850-evm: add SPI flash support ARM: davinci: da850: override SPI DT node device name ARM: davinci: da850: add SPI1 DT node spi/davinci: add DT binding documentation spi/davinci: no wildcards in DT compatible property ARM: davinci: da850: add EHRPWM & ECAP DT node ARM: davinci: da850: override mmc DT node device name ARM: davinci: da850: add mmc DT entries mmc: davinci_mmc: add DT support ARM: davinci: da850: add tps6507x regulator DT data ARM: regulator: add tps6507x device tree data ARM: davinci: remove test for undefined Kconfig macro ARM: davinci: mmc: derive version information from device name ARM: davinci: da850: add ECAP & EHRPWM clock nodes ARM: davinci: clk framework support for enable/disable functionality Signed-off-by:
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git://git.infradead.org/users/jcooper/linuxOlof Johansson authored
From Jason Cooper: mvebu dt for v3.10 round 4 - mvebu LPAE 64bit dts file changes * tag 'dt-3.10-4' of git://git.infradead.org/users/jcooper/linux : (52 commits) ARM: dts: mvebu: Convert mvebu device tree files to 64 bits ARM: dts: mvebu: introduce internal-regs node ARM: dts: mvebu: Convert all the mvebu files to use the range property ARM: dts: mvebu: move all peripherals inside soc ARM: dts: mvebu: fix cpus section indentation arm: mvebu: PCIe Device Tree informations for Armada XP GP arm: mvebu: PCIe Device Tree informations for Armada 370 DB arm: mvebu: PCIe Device Tree informations for Armada 370 Mirabox arm: mvebu: PCIe Device Tree informations for Armada XP DB arm: mvebu: PCIe Device Tree informations for OpenBlocks AX3-4 arm: mvebu: add PCIe Device Tree informations for Armada XP arm: mvebu: add PCIe Device Tree informations for Armada 370 ARM: mvebu: Align the internal registers virtual base to support LPAE ARM: mvebu: Limit the DMA zone when LPAE is selected arm: plat-orion: remove addr-map code arm: mach-mv78xx0: convert to use the mvebu-mbus driver arm: mach-orion5x: convert to use mvebu-mbus driver arm: mach-dove: convert to use mvebu-mbus driver arm: mach-kirkwood: convert to use mvebu-mbus driver arm: mach-mvebu: convert to use mvebu-mbus driver ... Signed-off-by:
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Manjunathappa, Prakash authored
Enable m25p64 SPI flash support on da850-EVM. Also add partition information of SPI flash. Signed-off-by:
Manjunathappa, Prakash <prakash.pm@ti.com> Signed-off-by:
Sekhar Nori <nsekhar@ti.com>
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Manjunathappa, Prakash authored
Populate OF_DEV_AUXDATA with desired device name expected by spi-davinci driver. Without this clk_get of spi-davinci DT driver fails. Signed-off-by:
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Manjunathappa, Prakash authored
Patch adds SPI1 DT node along with pinmux data. Signed-off-by:
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Murali Karicheri authored
Add binding documentation for spi-davinci module. [prakash.pm@ti.com: Follow DT naming convention for compatible property] Signed-off-by:
Murali Karicheri <m-karicheri2@ti.com> Acked-by:
Grant Likely <grant.likely@secretlab.ca> Signed-off-by:
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Manjunathappa, Prakash authored
Follow DT naming convention for compatible property of the blob. Use first chip name that introduced the specific version of the device. Signed-off-by:
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- Apr 15, 2013
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Gregory CLEMENT authored
In order to be able to use more than 4GB of RAM when the LPAE is activated, the dts must be converted in 64 bits. Only Armada XP is LPAE capable, but as it shares a common dtsi file with Armada 370, then the common file include the skeleton64. Thanks to the use of the overload capability of the device tree format, armada-370 include the 32 bit skeleton and all the armada 370 based dts can remain the same. This was heavily based on the work of Lior Amsalem. Signed-off-by:
Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by:
Jason Cooper <jason@lakedaemon.net>
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Gregory CLEMENT authored
Introduce a 'internal-regs' subnode, under which all devices are moved. This is not really needed for now, but will be for the mvebu-mbus driver. This generates a lot of code movement since it's indenting by one more tab all the devices. So it was a good opportunity to fix all the bad indentation. Signed-off-by:
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Gregory CLEMENT authored
This conversion will allow to keep 32 bits addresses for the internal registers whereas the memory of the system will be 64 bits. Later it will also ease the move of the mvebu-mbus driver to the device tree support. Signed-off-by:
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Thomas Petazzoni authored
reorganize the .dts and .dtsi files so that all devices are under the soc { } node (currently some devices such as the interrupt controller, the L2 cache and a few others are outside). Signed-off-by:Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by:
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Thomas Petazzoni authored
Align the cpu node indentation with the rest of the file [gc]: added a commit description Signed-off-by:
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Jason Cooper authored
Pulling in mvebu branches which contain changes to armada*.dts? files for LPAE conversion. mvebu soc changes for v3.10 - use the mvebu-mbus driver - prep for LPAE support Depends: - mvebu/cleanup (tags/cleanup_for_v3.10) - mvebu/drivers (tags/drivers_for_v3.10)
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Jason Cooper authored
pulling in mvebu branches which changes armada*.dts? files for LPAE changes mvebu fixes for v3.9 round 3 - Kirkwood - a couple of small fixes for the Iomega ix2-200 board (ether and led) - mvebu - allow GPIO button to work on Mirabox when running SMP -
Thomas Petazzoni authored
The Marvell Armada XP GP board has 3 physical full-size PCIe slots, so we enable the corresponding PCIe interfaces in the Device Tree. Signed-off-by:
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Thomas Petazzoni authored
The Marvell evaluation board (DB) for the Armada 370 SoC has 2 physical full-size PCIe slots, so we enable the corresponding PCIe interfaces in the Device Tree. Signed-off-by:
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Thomas Petazzoni authored
The Globalscale Mirabox platform uses one PCIe interface for an available mini-PCIe slot, and the other PCIe interface for an internal USB 3.0 controller. We add the necessary Device Tree informations to enable those two interfaces. Signed-off-by:
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Thomas Petazzoni authored
The Marvell evaluation board (DB) for the Armada XP SoC has 6 physicals full-size PCIe slots, so we enable the corresponding PCIe interfaces in the Device Tree. Signed-off-by:
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Thomas Petazzoni authored
The PlatHome OpenBlocks AX3-4 has an internal mini-PCIe slot that can be used to plug mini-PCIe devices. We therefore enable the PCIe interface that corresponds to this slot. Signed-off-by:
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Thomas Petazzoni authored
The Armada XP SoCs have multiple PCIe interfaces. The MV78230 has 2 PCIe units (one 4x or quad 1x, the other 1x only), the MV78260 has 3 PCIe units (two 4x or quad 1x and one 4x/1x), the MV78460 has 4 PCIe units (two 4x or quad 1x and two 4x/1x). We therefore add the necessary Device Tree informations to make those PCIe interfaces usable. Signed-off-by:
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Thomas Petazzoni authored
The Armada 370 SoC has two 1x PCIe 2.0 interfaces, so we add the necessary Device Tree informations to make these interfaces availabel. Signed-off-by:
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Lior Amsalem authored
In order to be able to support the LPAE, the internal registers virtual base must be aligned to 2MB. In LPAE section size is 2MB, in earlyprintk we map the internal registers and it must be section aligned. Signed-off-by:
Lior Amsalem <alior@marvell.com> Signed-off-by:
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Gregory CLEMENT authored
When LPAE is activated on Armada XP, all registers and IOs are still 32bit, the 40bit extension is on the CPU to DRAM path (windows) only. That means that all the DMA transfer are restricted to the low 32 bits address space. This is limitation is achieved by selecting ZONE_DMA. Signed-off-by:
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Thomas Petazzoni authored
Now that all Marvell EBU platforms have been converted to use the mvebu-mbus driver, we can remove the common plat-orion/addr-map.c code that isn't compiled anymore. Signed-off-by:
Arnd Bergmann <arnd@arndb.de> Signed-off-by:
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Thomas Petazzoni authored
This commit convers the mach-mv78xx0 sub-architecture to use the mvebu-mbus driver. We simply have to call mvebu_mbus_init() in the ->init_early() function, and modify the PCIe code so that it uses the new functions provided by mvebu-mbus to create the needed PCIe windows. Signed-off-by:
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Thomas Petazzoni authored
This commit migrates the mach-orion5x platforms to use the mvebu-mbus driver and therefore removes the Orion5x-specific addr-map code. The dove_init_early() function now initializes the mvebu-mbus driver by calling mvebu_mbus_init(). We also convert a number of orion5x_setup_xyz_win() calls to the appropriate mvebu_mbus_add_window() calls, as each board was doing its own setup for the NOR window or other devices. Ultimately, those devices will be probed from the DT. The common address decoding windows are now registered in the orion5x_setup_wins() function. It is worth noting that the four PCIe address decoding windows will ultimately no longer have to be registered here: it will be done automatically by the PCIe driver once Dove has been migrated to use the upcoming mvebu PCIe driver. Signed-off-by:
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Thomas Petazzoni authored
This commit migrates the mach-dove platforms to use the mvebu-mbus driver and therefore removes the Dove-specific addr-map code. The dove_init_early() function now initializes the mvebu-mbus driver by calling mvebu_mbus_init(). The address decoding windows are now registered in the dove_setup_cpu_wins() function. It is worth noting that the four PCIe address decoding windows will ultimately no longer have to be registered here: it will be done automatically by the PCIe driver once Dove has been migrated to use the upcoming mvebu PCIe driver. Signed-off-by:
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Thomas Petazzoni authored
This commit migrates the mach-kirkwood platforms to use the mvebu-mbus driver and therefore removes the Kirkwood-specific addr-map code. The kirkwood_init_early() function is now responsible for initializing the mvebu-mbus driver by calling mvebu_mbus_init(). The address decoding windows are now registered in the kirkwood_setup_wins() function. It is worth noting that the four PCIe address decoding windows will ultimately no longer have to be registered here: it will be done automatically by the PCIe driver once Kirkwood has been migrated to use the upcoming mvebu PCIe driver. Signed-off-by:
Andrew Lunn <andrew@lunn.ch> Acked-by:
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Thomas Petazzoni authored
The changes needed to migrate the mach-mvebu (Armada 370 and Armada XP) to the mvebu-mbus driver are fairly minimal, since not many devices currently supported on those SoCs use address decoding windows. The only one being the BootROM window, used to bring up secondary CPUs. However, this BootROM window needed for SMP brings an important requirement: the mvebu-mbus driver must be initialized at the ->early_init() time, otherwise the BootROM window cannot be setup early enough to be ready before the secondary CPUs are started. Signed-off-by:
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Jason Cooper authored
mvebu drivers for v3.10 - mvebu: mbus driver for kirkwood, dove, orion5x, mv78xx, and armada 370/xp
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