- Jan 21, 2017
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Marek Vasut authored
Add driver for IDT VersaClock 5 5P49V5923 and 5P49V5933 chips. These chips have two clock inputs, XTAL or CLK, which are muxed into single PLL/VCO input. In case of 5P49V5923, the XTAL in built into the chip while the 5P49V5923 requires external XTAL. The PLL feeds two fractional dividers. Each fractional divider feeds output mux, which allows selecting between clock from the fractional divider itself or from output mux on output N-1. In case of output mux 0, the output N-1 is instead connected to the output from the mux feeding the PLL. The driver thus far supports only the 5P49V5923 and 5P49V5933, while it should be easily extensible to the whole 5P49V59xx family of chips as they are all pretty similar. Signed-off-by:
Marek Vasut <marek.vasut@gmail.com> Cc: Michael Turquette <mturquette@baylibre.com> Reviewed-by:
Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Tested-by:
Laurent Pinchart <laurent.pinchart@ideasonboard.com> Cc: linux-renesas-soc@vger.kernel.org Signed-off-by:
Stephen Boyd <sboyd@codeaurora.org>
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Marek Vasut authored
Add bindings for IDT VersaClock 5 5P49V5923 and 5P49V5933 chips. These are I2C clock generators with optional clock source from either XTal or dedicated clock generator and, depending on the model, two or more clock outputs. Signed-off-by:
Rob Herring <robh@kernel.org> Reviewed-by:
Geert Uytterhoeven <geert+renesas@glider.be> Cc: devicetree@vger.kernel.org Cc: linux-renesas-soc@vger.kernel.org Signed-off-by:
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Stephen Boyd authored
Merge tag 'v4.11-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next Pull Rockchip clk updates from Heiko Stuebner: A new clock-type for the 1-2 muxes per soc that are for whatever reason controlled through the General Register Files, support for the rk3328 clock-controller (including a new pll-type) and the usual clock ids and some fixes. * tag 'v4.11-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: dt-bindings: clk: add rockchip,grf property for RK3399 clk: rockchip: use clock ids for memory controller parts on rk3066/rk3188 clk: rockchip: use rk3288 isp_in clock ids clk: rockchip: add clock ids for memory controller parts on rk3066/rk3188 clk: rockchip: add rk3288 isp_in clock ids clk: rockchip: Remove useless init of "grf" to -EPROBE_DEFER clk: rockchip: add clock controller for rk3328 dt-bindings: add bindings for rk3328 clock controller clk: rockchip: add dt-binding header for rk3328 clk: rockchip: add new pll-type for rk3328 clk: rockchip: describe aclk_vcodec using the new muxgrf type on rk3288 clk: rockchip: add a clock-type for muxes based in the grf
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git://linuxtv.org/snawrocki/samsungStephen Boyd authored
Pull Samsung clk updates from Sylwester Nawrocki: - addition of the CPU clock configuration data for Exynos4412 Prime SoC variant, - removal of driver for deprecated Exynos4415 SoC, - switching from the syscore to regular system sleep PM ops in the audio subsystem clocks controller driver, - updates of the definitions of some "Network On Chip" related clocks. * tag 'clk-v4.11-samsung' of git://linuxtv.org/snawrocki/samsung: clk: samsung: Remove Exynos4415 driver (SoC not supported anymore) clk: samsung: exynos-audss: Replace syscore PM with platform device PM clk: samsung: exynos5433: Set NoC (Network On Chip) clocks as critical clk: samsung: Add CPU clk configuration data for Exynos4412 Prime
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Lucas Stach authored
The LDB mux/gate layout has been fixed on QuadPlus, so there is no need to restrict the LDB mux changes on this hardware, as the erratum preventing this from working properly is gone. Signed-off-by:
Lucas Stach <l.stach@pengutronix.de> Reviewed-by:
Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by:
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Stephen Boyd authored
Merge tag 'clk-renesas-for-v4.11-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-next Pull renesas clk updates from Geert Uytterhoeven: - Add CAN and MSIOF related clocks for R-Car M3-W. * tag 'clk-renesas-for-v4.11-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers: clk: renesas: r8a7796: Add MSIOF controller clocks clk: renesas: r8a7796: Add CAN FD peripheral clock clk: renesas: r8a7796: Add CANFD clock clk: renesas: r8a7796: Add CAN peripheral clock
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- Jan 16, 2017
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Krzysztof Kozlowski authored
Support for Exynos4415 is going away because there are no internal nor external users. Since commit 46dcf0ff ("ARM: dts: exynos: Remove exynos4415.dtsi"), the platform cannot be instantiated so remove also the drivers. Signed-off-by:
Krzysztof Kozlowski <krzk@kernel.org> Acked-by:
Kukjin Kim <kgene@kernel.org> Signed-off-by:
Sylwester Nawrocki <s.nawrocki@samsung.com>
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- Jan 14, 2017
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Xing Zheng authored
Add support for rockchip,grf property which is used for GRF muxes on RK3399. Signed-off-by:
Xing Zheng <zhengxing@rock-chips.com> Reviewed-by:
Douglas Anderson <dianders@chromium.org> Acked-by:
Heiko Stuebner <heiko@sntech.de>
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Heiko Stuebner authored
Add the newly added clock ids to the clock entries of the rk3066/rk3188 clock driver. We won't be needing them in the kernel for a bit yet but as they're used in the new u-boot ddr setup code/dts we should make sure the clock ids stay identical and do not differ. Signed-off-by: -
Jacob Chen authored
Reference the newly added isp clock-ids in the clock-tree. Signed-off-by:
Jacob Chen <jacob-chen@iotwrt.com> Signed-off-by:
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Heiko Stuebner authored
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Heiko Stuebner authored
Add clock ids for the upctl and publ controllers used for ddr control. Signed-off-by:
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- Jan 13, 2017
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Jacob Chen authored
Add clock-ids for the isp block of the rk3288. Signed-off-by:
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Arnd Bergmann authored
The failure path in the newly added function tries to free an uninitialized pointer: drivers/clk/clk-stm32f4.c: In function 'stm32f4_rcc_init': drivers/clk/clk-stm32f4.c:1106:4: error: 'gate' may be used uninitialized in this function [-Werror=maybe-uninitialized] I'm adding an initialization to NULL here to make the kfree() succeed, and I'm also rearranging the cleanup so that the same kfree() is used for any error path, making the function slightly more robust against newly introduced bugs in the error handling. Fixes: daf2d117 ("clk: stm32f4: Add lcd-tft clock") Signed-off-by:
Arnd Bergmann <arnd@arndb.de> Acked-by:
Gabriel Fernandez <gabriel.fernandez@st.com> Signed-off-by:
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- Jan 10, 2017
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Stephen Boyd authored
* clk-fixes: clk/samsung: exynos542x: mark some clocks as critical
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Akinobu Mita authored
The CDCE925 is a member of the CDCE(L)9xx programmable clock generator family. There are also CDCE913, CDCE937, CDCE949 which have different number of PLLs and outputs. The clk-cdce925 driver supports only CDCE925 in the family. This adds support for the CDCE913, CDCE937, CDCE949, too. Signed-off-by:
Akinobu Mita <akinobu.mita@gmail.com> Acked-by:
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Zoran Markovic authored
Add definition of EBI2 clock used by MDM9615 NAND controller. Cc: Andy Gross <andy.gross@linaro.org> Cc: David Brown <david.brown@linaro.org> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: Rob Herring <robh+dt@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: linux-arm-msm@vger.kernel.org Cc: linux-soc@vger.kernel.org Cc: linux-clk@vger.kernel.org Cc: devicetree@vger.kernel.org Signed-off-by:
Zoran Markovic <zmarkovic@sierrawireless.com> Acked-by:
Neil Armstrong <narmstrong@baylibre.com> [sboyd@codeaurora.org: ebi2_clk halt bit is 24 not 23] Signed-off-by:
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Masahiro Yamada authored
This include was needed to suppress build error when this driver was initially merged because <linux/regmap.h> did not include <linux/delay.h> at that time. (developers' headache across sub-systems) The root cause has been fixed by commit adf08d48 ("regmap: include <linux/delay.h> from include/linux/regmap.h"), so this line can be dropped now. Signed-off-by:
Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by:
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Thomas Petazzoni authored
This commit adjusts the list of possible "Sample At Reset" values that define the CPU clock frequency of the AP806 (part of Marvell Armada 7K/8K) to the values that have been validated with the production chip. Earlier values were preliminary. Signed-off-by:
Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by:
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Stephen Boyd authored
* clk-hi3660: clk: hisilicon: Add clock driver for hi3660 SoC dt-bindings: Document the hi3660 clock bindings
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Zhangfei Gao authored
Add clock drivers for hi3660 SoC, this driver controls the SoC registers to supply different clocks to different IPs in the SoC. Signed-off-by:
Zhangfei Gao <zhangfei.gao@linaro.org> [sboyd@codeaurora.org: Simplify probe with function pointer] Signed-off-by:
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Zhangfei Gao authored
Add DT bindings documentation for hi3660 SoC clock. Signed-off-by:
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Marek Szyprowski authored
Some parent clocks of the Exynos542x clock blocks, which have separate power domains (like DISP, MFC, MSC, GSC, FSYS and G2D) must be always enabled to access any register related to power management unit or devices connected to it. For the time being, until a proper solution based on runtime PM is applied, mark those clocks as critical (instead of ignore unused or even no flags) to prevent disabling them. Signed-off-by:
Marek Szyprowski <m.szyprowski@samsung.com> Acked-by:
Chanwoo Choi <cw00.choi@samsung.com> Reviewed-by:
Javier Martinez Canillas <javier@osg.samsung.com> Tested-by: Javier Martinez Canillas <javier@osg.samsung.com> [Exynos5800 Peach Pi Chromebook] Signed-off-by:
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Geert Uytterhoeven authored
EPROBE_DEFER is not an error, hence printing an error message like clk: couldn't get clock 0 for /soc/display@feb00000 may confuse the user. Suppress error messages in case of probe deferral to fix this. Signed-off-by:
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Sudeep Holla authored
Currently we add the virtual cpufreq device unconditionally even when the SCPI DVFS clock provider node is disabled. This will cause cpufreq driver to throw errors when it gets initailised on boot/modprobe and also when the CPUs are hot-plugged back in. This patch fixes the issue by adding the virtual cpufreq device only if the SCPI DVFS clock provider is available and registered. Fixes: 9490f01e ("clk: scpi: add support for cpufreq virtual device") Reported-by:
Michał Zegan <webczat_200@poczta.onet.pl> Cc: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by:
Sudeep Holla <sudeep.holla@arm.com> Tested-by:
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Avaneesh Kumar Dwivedi authored
Add support to use reset control framework for resetting MSS with hexagon v56 1.5.0. Signed-off-by:
Avaneesh Kumar Dwivedi <akdwived@codeaurora.org> Reviewed-by:
Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by:
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Jun Nie authored
The audio related clock support is missing from the existing zx296718 clock driver. Let's add it, so that the upstream ZX SPDIF driver can work for HDMI audio support. Signed-off-by:
Jun Nie <jun.nie@linaro.org> Signed-off-by:
Shawn Guo <shawn.guo@linaro.org> [sboyd@codeaurora.org: Staticize some more structures] Signed-off-by:
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Shawn Guo authored
It adds the compatible string for zx296718 audio clock controller. Signed-off-by:
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Shawn Guo authored
Instead of using panic, we should give an error message and return error code when of_clk_add_hw_provider() call fails. Since we have error prompt for failures, the "init over" pr_info output isn't really necessary but becomes a debug noise. So let's clean it up along the way. Signed-off-by:
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Nicholas Mc Guire authored
The delay here is not in atomic context and does not seem critical with respect to precision, but usleep_range(min,max) with min==max results in giving the timer subsystem no room to optimize uncritical delays. Fix this by setting the range to 2000,3000 us. Fixes: commit f05259a6 ("clk: wm831x: Add initial WM831x clock driver") Signed-off-by:
Nicholas Mc Guire <hofrat@osadl.org> Acked-by:
Charles Keepax <ckeepax@opensource.wolfsonmicro.com> Signed-off-by:
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Nikita Yushchenko authored
On vf610, PLL1 and PLL2 have registers to configure fractional part of frequency multiplier. This patch adds support for these registers. This fixes "fast system clock" issue on boards where bootloader sets fractional multiplier for PLL1. Suggested-by:
Andrey Smirnov <andrew.smirnov@gmail.com> CC: Chris Healy <cphealy@gmail.com> Signed-off-by:
Nikita Yushchenko <nikita.yoush@cogentembedded.com> Tested-by:
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Jose Abreu authored
Init field must be cleared in driver probe as this structure is not dinamically allocated. If not, wrong flags can be passed to core. Signed-off-by:
Jose Abreu <joabreu@synopsys.com> Cc: Carlos Palminha <palminha@synopsys.com> Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: Michael Turquette <mturquette@baylibre.com> Cc: linux-clk@vger.kernel.org Cc: linux-kernel@vger.kernel.org Fixes: 923587aa ("clk/axs10x: Add I2S PLL clock driver") Signed-off-by:
Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/040cc9afdfa0e95ce7a01c406ff427ef7dc0c0fd.1481540717.git.joabreu@synopsys.com
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Stephen Boyd authored
* clk-qcom-rpm8974: clk: qcom: smd-rpmcc: Add msm8974 clocks * clk-stm32f4: clk: stm32f4: SDIO & 48Mhz clock management for STM32F469 board clk: stm32f4: Add SAI clocks clk: stm32f4: Add I2S clock clk: stm32f4: Add lcd-tft clock clk: stm32f4: Add post divisor for I2S & SAI PLLs clk: stm32f4: Add PLL_I2S & PLL_SAI for STM32F429/469 boards clk: stm32f4: Update DT bindings documentation * clk-ipq4019: clk: qcom: ipq4019: Add the cpu clock frequency change notifier clk: qcom: ipq4019: Add all the frequencies for apss cpu clk: qcom: ipq4019: correct sdcc frequency and parent name clk: qcom: ipq4019: Add the nodes for pcnoc clk: qcom: ipq4019: Add the apss cpu pll divider clock node clk: qcom: ipq4019: remove fixed clocks and add pll clocks * clk-fixes: clk: stm32f4: Use CLK_OF_DECLARE_DRIVER initialization method clk: renesas: mstp: Support 8-bit registers for r7s72100
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- Jan 07, 2017
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Douglas Anderson authored
When we used to defer setting the "grf" member to rockchip_clk_get_grf() it was important to init the "grf" member to an error value in rockchip_clk_init(). With recent changes, we now set "grf" right in rockchip_clk_init() (two lines below the place where we initted it). That makes the old init useless. Get rid of it. Fixes: 6f339dc2 ("clk: rockchip: lookup General Register Files in rockchip_clk_init") Signed-off-by:
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- Jan 05, 2017
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Elaine Zhang authored
Add the clock tree definition for the new rk3328 SoC. Signed-off-by:
Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by:
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Elaine Zhang authored
Add devicetree bindings for Rockchip cru which found on Rockchip SoCs. Signed-off-by:
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Heiko Stuebner authored
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Elaine Zhang authored
Add the dt-bindings header for the rk3328, that gets shared between the clock controller and the clock references in the dts. Add softreset ID for rk3328. Signed-off-by:
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- Jan 02, 2017
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Elaine Zhang authored
The rk3328's pll and clock are similar with rk3036's, it different with pll_mode_mask, the rk3328 soc pll mode only one bit(rk3036 soc have two bits) so these should be independent and separate from the series of rk3328s. Signed-off-by:
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Heiko Stuebner authored
With the newly introduced clk type for muxes in the grf we now can describe some missing clocks, like the aclk_vcodec that selects between aclk_vdpu and aclk_vepu based on a bit set in the general register files. Signed-off-by:
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