- Jul 26, 2014
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Mike Turquette authored
Merge tag 'sunxi-clocks-for-3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into clk-next-sunxi Allwinner clocks additions for 3.17 This pull request adds support for the clocks found in the newly supported Allwinner A23 clocks.
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Mike Turquette authored
Merge tag 'qcom-clocks-for-3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/galak/linux-qcom into clk-next-msm qcom clock changes for 3.17 These patches add support for a handful of Qualcomm's SoC clock controllers: APQ8084 gcc and mmcc, IPQ8064 gcc, and APQ8064. There's also a small collection of bug fixes that aren't critical -rc worthy regressions because the consumer drivers aren't present or using the buggy clocks and one optimization for HDMI.
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Mike Turquette authored
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Sylwester Nawrocki authored
This patch adds helper functions to configure clock parents and rates as specified through 'assigned-clock-parents', 'assigned-clock-rates' DT properties for a clock provider or clock consumer device. The helpers are now being called by the bus code for the platform, I2C and SPI busses, before the driver probing and also in the clock core after registration of a clock provider. Signed-off-by:
Sylwester Nawrocki <s.nawrocki@samsung.com> Acked-by:
Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by:
Mike Turquette <mturquette@linaro.org>
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- Jul 24, 2014
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Mike Turquette authored
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- Jul 16, 2014
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Stephen Boyd authored
The APQ8064 multimedia clock controller is fairly similar to the 8960 multimedia clock controller, except that gfx2d0/1 has been removed and the gfx3d frequency is slightly faster when using the newly introduced PLL15. We also add vcap clocks and a couple new TV clocks. Signed-off-by:Stephen Boyd <sboyd@codeaurora.org>
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Stephen Boyd authored
Some SR type PLLs need to be configured for a certain rate when linux boots. Add support for these types of PLLs so that we can program PLL15's rate on apq8064. Signed-off-by: -
Stephen Boyd authored
The mdp_lut_clk isn't a child of the mdp_clk. Instead it's the child of the mdp_src clock. Fix it. Fixes: 6d00b56f "clk: qcom: Add support for MSM8960's multimedia clock controller (MMCC)" Signed-off-by:
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Stephen Boyd authored
Sometimes we need to program PLLs with a fixed rate configuration during driver probe. Doing this after we register the PLLs with the clock framework causes the common clock framework to assume the rate of the PLLs are 0. This causes all sorts of problems for rate recalculations because the common clock framework caches the rate once at registration time unless a flag is set to always recalculate the rates. Split the qcom_cc_probe() function into two pieces, map and everything else, so that drivers which need to configure some PLL rates or otherwise twiddle bits in the clock controller can do so before registering clocks. This allows us to properly detect the rates of PLLs that are programmed at boot. Fixes: 49fc825f "clk: qcom: Consolidate common probe code" Signed-off-by:
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Stephen Boyd authored
Clocks that don't have a pre-divider don't list any pre-divider in their frequency tables, but their tables are initialized using aggregate initializers. Use tagged initializers so we properly assign the m and n values for each frequency. Furthermore, the mmcc_pxo_pll8_pll2_pll3 array improperly mapped the second element to pll2 instead of pll8, causing the clock driver to recalculate the wrong rate for any clocks using this array along with a rate that uses pll2. Plus the .num_parents field is 3 instead of 4 so you can't even switch the parent to pll3. Finally I noticed that the jpegd clock improperly indicates that the pre-divider width is only 2, when it's actually 4 bits wide. Fixes: 6d00b56f "clk: qcom: Add support for MSM8960's multimedia clock controller (MMCC)" Tested-by:
Rob Clark <robdclark@gmail.com> Signed-off-by:
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Stephen Boyd authored
In the case of HDMI clocks, we want to bypass the RCG's ability to divide the output clock and pass through the parent HDMI PLL rate. Add a simple set of clk_ops to configure the RCG to do this. This removes the need to keep adding more frequency entries to the tv_src clock whenever we want to support a new rate. Tested-by:
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Kumar Gala authored
Add a driver for the global clock controller found on IPQ8064 based platforms. This should allow most non-multimedia device drivers to probe and control their clocks. This is currently missing clocks for USB HSIC and networking devices. Signed-off-by:
Kumar Gala <galak@codeaurora.org> Signed-off-by:
Andy Gross <agross@codeaurora.org> Signed-off-by:
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Georgi Djakov authored
Add support for the multimedia clock controller found on the APQ8084 based platforms. This will allow the multimedia device drivers to control their clocks. Signed-off-by:
Georgi Djakov <gdjakov@mm-sol.com> [sboyd: Rework parent mapping to avoid conflicts] Signed-off-by:
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- Jul 15, 2014
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Chen-Yu Tsai authored
This patch adds "allwinner,sun8i-a23-apb0-gates-clk", a A23 specific compatible to the sun6i-a31-apb0-gates clock driver, along with the gate bitmap. Signed-off-by:
Chen-Yu Tsai <wens@csie.org> Signed-off-by:
Maxime Ripard <maxime.ripard@free-electrons.com>
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Chen-Yu Tsai authored
sun6i-apb0-gates uses the "clock-indices" DT property to indicate valid gate bits or holes in between. However, the rest of sunxi clock drivers use bitmaps for this purpose. This patch modifies sun6i-apb0-gates to use bitmaps as well, to be consistent with the sunxi platform. Also add the missing call to clk_register_clkdev, so system clock lookups will work. Signed-off-by:
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- Jul 14, 2014
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Heiko Stübner authored
All known Rockchip SoCs have a reset controller in their CRUs, so it's helpful to have the reset controller framework selected by default, only be deselected by the user in special cases. Signed-off-by:
Heiko Stuebner <heiko@sntech.de> Acked-By:
Max Schwarz <max.schwarz@online.de> Tested-By:
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Heiko Stübner authored
Add the clock tree definition for the new rk3288 SoC. Signed-off-by:
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Heiko Stübner authored
This adds the dt-binding documentation for the clock and reset unit found on Rockchip rk3288 SoCs. Signed-off-by:
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Heiko Stübner authored
This adds a clock driver that handles the specific muxes, dividers and gates of rk3188 and rk3066 SoCs. The structure of the clock list resembles the arrangement of their counterparts in the clock architecture diagrams found in the SoC documentation. Clocks exported to the clock provider are currently limited to well known or measured ones. So additional clock exports may be necessary in the future. Signed-off-by:
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Heiko Stübner authored
This add bindings documentation for the clock and reset unit found on rk3188 and rk3066 SoCs from Rockchip. Also deprecate the old gate clock binding, as these shouldn't be used in the future. Signed-off-by:
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Heiko Stübner authored
All Rockchip SoCs at least down to the ARM9-based RK28xx include the reset- controller for SoC peripherals in their clock controller. While the older SoCs (ARM9 and Cortex-A8) use a regular scheme to change register values, the Cortex-A9 SoCs use a hiword-mask making locking unecessary. To be compatible with both schemes the reset controller takes a flag to decide which scheme to use, similar to the other HIWORD_MASK flags used in the clock framework. Signed-off-by:
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Heiko Stübner authored
All known Rockchip SoCs down to the RK28xx (ARM9) use a similar pattern to handle their plls: |--\ xin32k ----------------|mux\ xin24m -----| pll |----|pll|--- pll output \---------------|src/ |--/ The pll output is sourced from 1 of 3 sources, the actual pll being one of them. To change the pll frequency it is imperative to remux it to another source beforehand. This is done by adding a clock-listener to the pll that handles the remuxing before and after the rate change. The output mux is implemented as a separate clock to make use of already existing common-clock features for disabling the pll if one of the other two sources is used. Signed-off-by: -
Heiko Stübner authored
This adds infrastructure for registering clock branches. On Rockchip SoCs most clock branches are a combination of mux,divider and gate components, thus a composite clock is used when appropriate. Clock branches are supposed to be declared in an array using the COMPOSITE* or MUX, etc makros defined in the header and then registered using rockchip_clk_register_branches. Signed-off-by:
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Mike Turquette authored
The function pointer population and sanity checking logic got a bit ugly with the advent of the .determine_rate callback. Clean it up. Signed-off-by: -
Heiko Stübner authored
This allows readl-only composite clocks by making mux_ops->set_parent and divider_ops->round_rate/set_rate optional. Signed-off-by:
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Boris BREZILLON authored
In case the rate_hw does not implement determine_rate, but only round_rate we fallback to best_parent selection if mux_hw is present and support reparenting. This also fixes a rate calculation problem when using the standard div and mux ops, as in this case currently only the mux->determine_rate is used in the composite rate calculation. So when for example the composite clock has two parents at 600 and 800MHz, the requested rate is 75MHz, which the divider could provide, without this change the rate would be set 600MHz ignoring the divider completely. This may be way out of spec for the component. Signed-off-by:
Boris BREZILLON <b.brezillon@overkiz.com> Signed-off-by:
Gabriel Fernandez <gabriel.fernandez@linaro.org> Signed-off-by:
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- Jul 13, 2014
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Mike Turquette authored
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Thomas Gleixner authored
The uarts only work when the parent is ras_ahb_clk. The stale 3.5 based ST tree does this in the board file. Add it to the clk init function. Not pretty, but the mess there is amazing anyway. Signed-off-by:
Thomas Gleixner <tglx@linutronix.de> Acked-by:
Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by:
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Thomas Gleixner authored
The control register is at offset 0x10, not 0x0. This is wreckaged since commit 5df33a62 (SPEAr: Switch to common clock framework). Signed-off-by:
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- Jul 12, 2014
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Georgi Djakov authored
Add the necessary clocks for SATA, PCIe and UFS to the APQ8084 global clock controller (GCC). This will allow the above device drivers to control their clocks. Signed-off-by:
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Georgi Djakov authored
This patch adds support for the global clock controller found on the APQ8084 based devices. This includes UART, I2C, SPI etc. Signed-off-by:
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Georgi Djakov authored
Add the compatible string for the APQ8084 global clock controller to the clock binding documentation. Signed-off-by:
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Stephen Boyd authored
Add in the handful of new clocks and introduce a new reset table with the few new resets. Signed-off-by: -
Srinivas Kandagatla authored
This patch adds clocks necessary for SD card controller on apq8064 SOC. Without this patch the clocks are not visible to the sdcc driver. Signed-off-by:
Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Reviewed-by:
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- Jul 11, 2014
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Pratyush Anand authored
Follow dt clock naming convention for PCIe clocks. Signed-off-by:
Pratyush Anand <pratyush.anand@st.com> Acked-by:
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- Jul 08, 2014
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Mike Turquette authored
Merge tag 'tegra-clk-3.17-1' of git://nv-tegra.nvidia.com/user/pdeschrijver/linux into clk-next-tegra tegra clk updates for 3.17 including PLLE fixes for xusb
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Mikko Perttunen authored
Use a sequence for enabling hardware control of the SATA PLL that works both when using the SATA lane with SATA and when using it with XUSB. Signed-off-by:Mikko Perttunen <mperttunen@nvidia.com>
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- Jul 07, 2014
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Chen-Yu Tsai authored
sun6i-a31-apb0-gates supports using clock-indices for holes between individual gates. However, the driver passes the number of gates registered in clk_data->clk_num, which of_clk_src_onecell_get uses to recognize the range of valid indices a consumer can use. This patch makes the driver pass the maximum gate index + 1, so of_clk_src_onecell_get does not complain about indices greater than gates registered. This was tested on the A23 SoC, which has a similar APB0 clock, but has holes for gates to removed IP blocks. Signed-off-by:
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Chen-Yu Tsai authored
The A23 has an almost identical PRCM clock tree. The difference in the APB0 clock is the smallest divisor is 1, instead of 2. This patch adds a separate sun8i-a23-apb0-clk driver to support it. Signed-off-by:
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- Jul 04, 2014
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Chen-Yu Tsai authored
The clock control unit on the A23 is similar to the one found on the A31. The AHB1, APB1, APB2 gates on the A23 are almost identical to the ones on the A31, but some outputs are missing. The main CPU PLL (PLL1) however is like that on older Allwinner SoCs, such as the A10 or A20, but the N factor starts from 1 instead of 0. This patch adds support for PLL1 and all the basic clock muxes and gates. Signed-off-by:
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