- Mar 27, 2018
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Icenowy Zheng authored
The Allwinner H6 SoC have its pin controllers with the first IRQ-capable GPIO bank at IRQ bank 1 and the second bank at IRQ bank 5. Change the current code that uses IRQ bank base to a IRQ bank map, in order to support the case that holes exist among IRQ banks. Signed-off-by:
Icenowy Zheng <icenowy@aosc.io> Acked-by:
Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by:
Linus Walleij <linus.walleij@linaro.org>
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Icenowy Zheng authored
The Allwinner H6 SoC have its pin controllers with the first IRQ-capable GPIO bank at IRQ bank 1 and the second bank at IRQ bank 5. Some refactors in the sunxi pinctrl framework are needed. This commit introduces a IRQ bank conversion function, which replaces the "(bank_base + bank)" code in IRQ register access. Signed-off-by:
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Icenowy Zheng authored
As the new H6 SoC has holes in the IRQ registers, refactor the IRQ related register function for getting the full pinctrl desc structure. Signed-off-by:
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Fabio Estevam authored
platform_driver does not need to set the owner field, as this will be populated by the driver core. Generated by scripts/coccinelle/api/platform_no_drv_owner.cocci. Signed-off-by:
Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by:
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Katsuhiro Suzuki authored
This patch divides large pin-mux group 'aio' of UniPhier LD11/LD20 to 2 groups as following: aout1 : 8ch I2S output: AO1DACCK, AO1BCK, AO1LRCK, AO1D[0-2] aoutiec1: S/PDIF output : AO1IEC, AO1ARC Signed-off-by:
Katsuhiro Suzuki <suzuki.katsuhiro@socionext.com> Acked-by:
Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by:
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Katsuhiro Suzuki authored
The UniPhier PXs2 SoC audio core use following 25 pins: ain1 : 2ch I2S input : AI1ADCCK, AI1BCK, AI1D0, AI1LRCK ain2 : 8ch I2S input : AI2ADCCK, AI2BCK, AI2D[0-3], AI2LRCK ainiec1 : S/PDIF input : XIRQ17 (for AO1IEC) aout2 : 8ch I2S output: AO2BCK, AO2D0, AO2DACCK, AO2LRCK PORT226, 227, 230 (for AO2D[1-3]) aout3 : 2ch I2S output: AO3BCK, AO3DMIX, AO3DACCK, AO3LRCK aoutiec1: S/PDIF output : PORT132(for AO1IEC) aoutiec2: S/PDIF output : AO2IEC Signed-off-by:
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- Mar 26, 2018
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Daniel Kurtz authored
In certain cases interrupt enablement will be delayed relative to when the InterruptEnable bits are written. One example of this is when a GPIO's "debounce" logice is first enabled. After enabling debounce, there is a 900 us "warm up" period during which InterruptEnable[0] (bit 11) will read as 0 despite being written 1. During this time InterruptSts will not be updated, nor will interrupts be delivered, even if the GPIO's interrupt configuration has been written to the register. To work around this delay, poll the InterruptEnable bits after setting them to ensure interrupts have truly been enabled in hardware before returning from the irq_enable handler. Signed-off-by:
Daniel Kurtz <djkurtz@chromium.org> Signed-off-by:
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Alexandre Belloni authored
Bits have to be cleared in DEVCPU_GCB:GPIO:GPIO_OE for input and set for output. ocelot_gpio_set_direction() got it wrong and this went unnoticed when the driver was reworked. Reported-by:
Gregory Clement <gregory.clement@bootlin.com> Signed-off-by:
Alexandre Belloni <alexandre.belloni@bootlin.com> Acked-by:
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Zhiyong Tao authored
This patch fixes check warnings. Signed-off-by:
Zhiyong Tao <zhiyong.tao@mediatek.com> Signed-off-by:
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Zhiyong Tao authored
For generic pins, parameter "arg" is 0 or 1. For special pins, bias-disable is set by R0R1, so we need transmited "00" to set bias-disable When we set "bias-disable" as high-z property, the parameter should be "MTK_PUPD_SET_R1R0_00". Signed-off-by:
Sean Wang <sean.wang@mediatek.com> Signed-off-by:
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Zhiyong Tao authored
The commit includes mt2712 pinctrl driver. Signed-off-by:
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David Lechner authored
This fixes pcs_request_gpio() in the pinctrl-single driver when bits_per_mux != 0. It appears this was overlooked when the multiple pins per register feature was added. Fixes: 4e7e8017 ("pinctrl: pinctrl-single: enhance to configure multiple pins of different modules") Signed-off-by:
David Lechner <david@lechnology.com> Acked-by:
Tony Lindgren <tony@atomide.com> Signed-off-by:
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- Mar 23, 2018
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Bai Ping authored
Add pinctrl driver support for imx6sll. Signed-off-by:
Bai Ping <ping.bai@nxp.com> Acked-by:
Shawn Guo <shawnguo@kernel.org> Acked-by:
Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by:
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Bai Ping authored
Add pinctrl binding doc update for imx6sll. Signed-off-by:
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Javier Arteaga authored
Allows querying GPIO direction from the pad config register. If the pad is not in GPIO mode, return an error. Signed-off-by:
Javier Arteaga <javier@emutex.com> Reviewed-by:
Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by:
Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by:
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Masahiro Yamada authored
These configs select MFD_SYSCON, but do not depend on HAS_IOMEM. Compile testing on architecture without HAS_IOMEM causes "unmet direct dependencies" in Kconfig phase. Detected by "make ARCH=score allyesconfig". Signed-off-by:
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Gustavo A. R. Silva authored
Assign true or false to boolean variables instead of an integer value. This issue was detected with the help of Coccinelle. Signed-off-by:
Gustavo A. R. Silva <gustavo@embeddedor.com> Signed-off-by:
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Andre Przywara authored
The Allwinner pinctrl device tree binding suggests that a clock named "apb" would drive the pin controller IP. However (for legacy reasons) we rely on this clock actually being the first clock defined. Since named clocks can be in any order, let's explicitly check for a clock called "apb" if there is more than one clock referenced. Kudo to Maxime for suggesting this much more elegant approach. Signed-off-by:
Andre Przywara <andre.przywara@arm.com> Acked-by:
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Linus Walleij authored
The U8540 was an evolved version of the U8500, but it was never mass produced or put into products, only reference designs exist. The upstream support was never completed and it is unlikely that this will happen so drop the support for now to simplify maintenance of the U8500. Cc: Loic Pallardy <loic.pallardy@st.com> Signed-off-by: -
Linus Walleij authored
Merge tag 'sh-pfc-for-v4.17-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: sh-pfc: Updates for v4.17 (take two) - Add USB pin groups on R-Car M3-N, - Add support for the new R-Car V3H SoC, - Add EtherAVB pin groups on R-Car V3M, - Miscellaneous fixes and cleanups.
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- Mar 22, 2018
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Ulrich Hecht authored
Use union vin_data and VIN_DATA_PIN_GROUP() to reduce redundancies in pin definitions. Signed-off-by:
Ulrich Hecht <ulrich.hecht+renesas@gmail.com> Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be>
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Ulrich Hecht authored
Use union vin_data and VIN_DATA_PIN_GROUP() to reduce redundancies in pin definitions. Signed-off-by:
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Ulrich Hecht authored
Use union vin_data and VIN_DATA_PIN_GROUP() to reduce redundancies in pin definitions. Signed-off-by:
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Ulrich Hecht authored
RGB666 has a pin assignment that differs from the other formats. Fixes: fbd452ae ("pinctrl: sh-pfc: r8a77995: Add VIN4 pins, groups and function") Signed-off-by:
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Ulrich Hecht authored
RGB666 has a pin assignment that differs from the other formats. Fixes: 8db6cbab ("pinctrl: sh-pfc: r8a7796: Add VIN4, VIN5 pins, groups and functions") Signed-off-by:
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Ulrich Hecht authored
RGB666 has a pin assignment that differs from the other formats. Fixes: 6b4de408 ("pinctrl: sh-pfc: r8a7795: Add VIN4, VIN5 pins, groups and functions") Signed-off-by:
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Geert Uytterhoeven authored
On other Renesas SoCs, the pin group for the MDIO bus is named "mdio" instead of "mdc". Fix the inconsistency, while retaining backwards compatibility with old DTBs using a pin group alias. Fixes: 66abd968 ("pinctrl: sh-pfc: r8a77995: Add EthernetAVB pins, groups and functions") Signed-off-by:
Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
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Geert Uytterhoeven authored
On other Renesas SoCs, the pin group for the MDIO bus is named "mdio" instead of "mdc". Fix the inconsistency, while retaining backwards compatibility with old DTBs using a pin group alias. Fixes: fa3e8b71 ("pinctrl: sh-pfc: r8a77965: Add EtherAVB groups/functions") Signed-off-by:
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Geert Uytterhoeven authored
On other Renesas SoCs, the pin group for the MDIO bus is named "mdio" instead of "mdc". Fix the inconsistency, while retaining backwards compatibility with old DTBs using a pin group alias. Fixes: 41397032 ("pinctrl: sh-pfc: r8a7796: Add group for AVB MDIO and MII pins") Fixes: 9c99a63e ("pinctrl: sh-pfc: r8a7796: Add EtherAVB pins, groups and functions") Signed-off-by:
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Geert Uytterhoeven authored
On other Renesas SoCs, the pin group for the MDIO bus is named "mdio" instead of "mdc". Fix the inconsistency, while retaining backwards compatibility with old DTBs using a pin group alias. Fixes: b25719eb ("pinctrl: sh-pfc: r8a7795: Add group for AVB MDIO and MII pins") Fixes: 819fd4bf ("pinctrl: sh-pfc: r8a7795: add EtherAVB support") Signed-off-by:
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Geert Uytterhoeven authored
On other Renesas SoCs, the pin group for the MDIO bus is named "mdio" instead of "mdc". Fix the inconsistency, while retaining backwards compatibility with old DTBs using a pin group alias. Fixes: 30c078de ("pinctrl: sh-pfc: r8a7795: Add EtherAVB pins, groups and function") Signed-off-by:
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Geert Uytterhoeven authored
Add a macro to refer to another pin group with a different name. This will be used to rename wrongly-named pin groups, while retaining backwards compatibility with old DTBs. Signed-off-by:
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Geert Uytterhoeven authored
The pin controller drivers for all R-Car Gen2 SoCs have entries for the EtherAVB TX_ER pins in their EtherAVB MII groups, except on R-Car H2. Add the missing pin to restore consistency. Note that technically TX_ER is an optional signal in the MII bus, and thus could have its own group, but this is currently not supported by any R-Car Gen2 pin controller driver. Fixes: 19ef697d ("sh-pfc: r8a7790: add EtherAVB pin groups") Signed-off-by:
Simon Horman <horms+renesas@verge.net.au>
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- Mar 14, 2018
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Sergei Shtylyov authored
Add the EtherAVB pin groups to the R8A77970 PFC driver. Signed-off-by:
Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by:
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- Mar 09, 2018
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Sergei Shtylyov authored
Add the PFC support for the R8A77980 SoC including pin groups for some on-chip devices such as AVB, CAN-FD, GETHER, [H]SCIF, I2C, INTC-EX, MMC, MSIOF, PWM, and VIN... Based on the original (and large) patch by Vladimir Barinov. Signed-off-by:
Vladimir Barinov <vladimir.barinov@cogentembedded.com> Signed-off-by:
Rob Herring <robh@kernel.org> Signed-off-by:
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Sergei Shtylyov authored
They follow the style of the existing PORT_GP_CFG_<n>() macros and will be used by a follow-up patch for the R8A77980 SoC. Based on the original (and large) patch by Vladimir Barinov. Signed-off-by:
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- Mar 05, 2018
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Takeshi Kihara authored
This patch adds USB30 (USB3.0 host) pin, group and function to the R8A77965 SoC. Signed-off-by:
Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by:
Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by:
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Takeshi Kihara authored
This patch adds USB{0,1} (USB2.0 host) pins, groups and functions to the R8A77965 SoC. Signed-off-by:
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- Mar 02, 2018
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Manivannan Sadhasivam authored
Add pinctrl bindings for Actions Semi S900 SoC Signed-off-by:
Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by:
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Linus Walleij authored
Merge tag 'sh-pfc-for-v4.17-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: sh-pfc: Updates for v4.17 - Add DU and VIN pin groups on R-Car D3, - Add HDMI, TMU, and VIN pin groups on R-Car H3 and M3-W, - Add support for the new R-Car M3-N SoC, - Small fixes and cleanups.
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