- Jul 31, 2014
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David Rientjes authored
The enable_apic_mode() apic callback is never called, so remove it. Signed-off-by:
David Rientjes <rientjes@google.com> Link: http://lkml.kernel.org/r/alpine.DEB.2.02.1407302352320.17503@chino.kir.corp.google.com Signed-off-by:
H. Peter Anvin <hpa@zytor.com>
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David Rientjes authored
Since commit b5660ba7 ("x86, platforms: Remove NUMAQ") removed NUMAQ, the setup_portio_remap() apic callback has been obsolete. Remove it. Signed-off-by:
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David Rientjes authored
Since commit b5660ba7 ("x86, platforms: Remove NUMAQ") removed NUMAQ, the multi_timer_check() apic callback has been obsolete. Remove it. Signed-off-by:
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David Rientjes authored
noop_check_apicid_used() has the same implementation as default_check_apicid_used() in the standard header file, so replace the former with the latter. Signed-off-by:
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David Rientjes authored
The check_apicid_present() apic callback is never called, so remove it and functions that implement it. Signed-off-by:
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David Rientjes authored
Since commit b5660ba7 ("x86, platforms: Remove NUMAQ") removed NUMAQ, the mps_oem_check() apic callback has been obsolete. Remove it. This allows generic_mps_oem_check() to be removed as well. Signed-off-by:
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David Rientjes authored
Since commit b5660ba7 ("x86, platforms: Remove NUMAQ") removed NUMAQ, the smp_callin_clear_local_apic() apic callback has been obsolete. Remove it. Signed-off-by:
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David Rientjes authored
The trampoline_phys_{high,low} members of struct apic are always initialized to DEFAULT_TRAMPOLINE_PHYS_HIGH and TRAMPOLINE_PHYS_LOW, respectively. Hardwire the constants and remove the unneeded members. Signed-off-by: -
David Rientjes authored
Since commit b5660ba7 ("x86, platforms: Remove NUMAQ") removed NUMAQ, the x86_32_numa_cpu_node() apic callback has been obsolete. Remove it. Signed-off-by:
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- Jul 15, 2014
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Jiang Liu authored
Commit 9f354b02 "x86, irq: Clean up unused IOAPIC interface" kills interface io_apic_set_pci_routing(), so change arch/x86/platform/ intel-mid/device_libs/platform_wdt.c to use new interfaces. Due to hardware resource restriction, this patch only passes compilation without functional tests. Signed-off-by:
Jiang Liu <jiang.liu@linux.intel.com> Acked-by:
David Cohen <david.a.cohen@linux.intel.com> Cc: Tony Luck <tony.luck@intel.com> Cc: Tang Feng <feng.tang@intel.com> Cc: Yinghai Lu <yinghai@kernel.org> Cc: H. Peter Anvin <hpa@zytor.com> Cc: Ingo Molnar <mingo@redhat.com> Cc: Tony Luck <tony.luck@intel.com> Link: http://lkml.kernel.org/r/1403490643-26187-1-git-send-email-jiang.liu@linux.intel.com Signed-off-by:
Thomas Gleixner <tglx@linutronix.de>
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- Jul 14, 2014
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Oren Twaig authored
When a vSMP Foundation box is detected, the function apic_cluster_num() counts the number of APIC clusters found. If more than one found, a multi board configuration is assumed, and TSC marked as unstable. This behavior is incorrect as vSMP Foundation may use processors from single node only, attached to memory of other nodes - and such node may have more than one APIC cluster (typically any recent intel box has more than single APIC_CLUSTERID(x)). To fix this, we simply remove the code which detects a vSMP Foundation box and affects apic_is_clusted_box() return value. This can be done because later the kernel checks by itself if the TSC is stable using the check_tsc_sync_[source|target]() functions and marks TSC as unstable if needed. Acked-by:
Shai Fultheim <shai@scalemp.com> Signed-off-by:
Oren Twaig <oren@scalemp.com> Link: http://lkml.kernel.org/r/1404036068-11674-1-git-send-email-oren@scalemp.com Signed-off-by:
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- Jun 22, 2014
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Jiang Liu authored
Now we have completely switched to irqdomain, so clean up transition code in IOAPIC drivers. Signed-off-by:
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Jiang Liu authored
Release IOAPIC pin associated with PCI device when the PCI device is disabled. Signed-off-by:
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Jiang Liu authored
Release IOAPIC pin associated with PCI device when the PCI device is disabled. Signed-off-by:
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Jiang Liu authored
Release IOAPIC pin associated with PCI device when the PCI device is disabled. Signed-off-by:
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Jiang Liu authored
Release IOAPIC pin associated with PCI device when the PCI device is disabled. Signed-off-by:
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Jiang Liu authored
Introduce function mp_unmap_irq() to release IOAPIC IRQ when IRQ is not used any more, which will typically called by pcibios_disabled_irq. And function mp_irqdomain_unmap() is a common implementation of irq_domain_ops.unmap for IOAPIC. Signed-off-by:
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Jiang Liu authored
On startup, setup_IO_APIC_irqs() will program all IOAPIC pins for ISA IRQs. Later when mp_map_pin_to_irq() is called, it just returns ISA IRQ number without programming corresponding IOAPIC pin. This patch consolidates the way to program IOAPIC pins for both ISA and non-ISA IRQs into mp_map_pin_to_irq() as below: 1) For ISA IRQs, mp_irqs array is used to map IOAPIC pin to IRQ and mp_irqdomain_map() is used to actually program the pin. 2) For non-ISA IRQs, irqdomain is used to map IOAPIC pin to IRQ, and mp_irqdomain_map() is also used to actually program the pin. Signed-off-by:
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Jiang Liu authored
Now we have converted all x86 platforms to use the common irqdomain map interface. There's no caller of io_apic_set_pci_routing(), setup_IO_APIC_irq_extra() and io_apic_setup_irq_pin_once() any more, so kill them. Signed-off-by:
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Jiang Liu authored
Refine devicetree to use common irqdomain map interface to program IOAPIC pins, so we can unify the callsite to progam IOAPIC pins. Signed-off-by:
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Jiang Liu authored
Refine SFI to use common irqdomain map interface to program IOAPIC pins, so we can unify the callsite to progam IOAPIC pins. Signed-off-by:
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Jiang Liu authored
Refine mpparse to use common irqdomain map interface to program IOAPIC pins, so we can unify the callsite to progam IOAPIC pins. Signed-off-by:
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Jiang Liu authored
Refine ACPI to use common irqdomain map interface to program IOAPIC pins, so we can unify the callsite to progam IOAPIC pins. Signed-off-by:
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Jiang Liu authored
Currently there are multiple entries to program IOAPIC pins, such as io_apic_setup_irq_pin_once(), io_apic_set_pci_routing() and setup_IO_APIC_irq_extra() etc. This patch introduces two functions to help consolidate the code to program IOAPIC pins. Function mp_set_pin_attr() is used to optionally set trigger, polarity and NUMA node property for an IOAPIC pin. If mp_set_pin_attr() is not invoked for a pin, the default configuration from BIOS will be used. Function mp_irqdomain_map() is an common implementation of irqdomain map() operation. It figures out attribures for pin and then actually programs the IOAPIC pin. We hope this will be the only entrance for programming IOAPIC pin. And the flow will: 1) caller such as xxx_pci_irq_enable figures out pin attributes. 2) Invoke mp_set_pin_attr() to set attributes for a pin. If the pin has already bin programmed, mp_set_pin_attr() will aslo detects attribute confictions. 3) Invoke mp_map_pin_to_irq() 3.1) If IRQ has already been assigned, return irq_find_mapping() 3.2) Else irq_create_mapping() ->irq_domain_associate() ->mp_irqdomain_map() ->io_apic_setup_irq_pin() So every pin will only programmed once by mp_irqdomain_map(), so we could kill io_apic_setup_irq_pin_once(), io_apic_set_pci_routing() and setup_IO_APIC_irq_extra() etc. Signed-off-by:
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Jiang Liu authored
Now the ioapic driver provides a common interface to create irqdomain, so replace the private implementation. Signed-off-by:
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Jiang Liu authored
Enhance SFI to provide basic support of irqdomain with identity mapping between GSIs and IRQs. Some Intel MID platforms assumes identity mapping between GSI and IRQ, so we can't dynamically allocate IRQ number on demand. Signed-off-by:
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Jiang Liu authored
Enhance mpparse to provide basic support of irqdomain. Signed-off-by:
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Jiang Liu authored
Enhance ACPI driver to provide basic irqdomain support for IOAPIC. We will build identity mapping for IOAPICs hosting legacy IRQs, otherwise dynamically allocate IRQ numbers for IOAPIC pins on demand. Signed-off-by:
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Jiang Liu authored
Enhance function mp_register_ioapic() to support irqdomain. When registering IOAPIC, caller may provide callbacks and parameters for creating irqdomain. The IOAPIC core will create irqdomain later if caller has passed in corresponding parameters. Signed-off-by:
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Jiang Liu authored
Currently x86 support identity mapping between GSI(IOAPIC pin) and IRQ number, so continous IRQs at low end are statically allocated to IOAPICs at boot time. This design causes trouble to support IOAPIC hotplug. This patch implements basic mechanism to dynamically allocate IRQ on demand for IOAPIC pins by using irqdomain framework. It first adds several fields into struct ioapic to support irqdomain. Then it implements an algorithm to dynamically allocate IRQ number for IOAPIC pins on demand. Currently it supports three types of irqdomain: 1) LEGACY: used to support IOAPIC hosting legacy IRQs and building identity mapping for legacy IRQs. A speical case, we dynamically allocate IRQ number for IOAPIC pin which has GSI number below nr_legacy_irqs() but isn't legacy IRQ. This is for backward compatibility and avoid regression. 2) STRICT: build identity mapping between GSI and IRQ nubmer. 3) DYNAMIC: dynamically allocate IRQ number for IOAPIC pin on demand. Legacy(ISA) IRQs is not managed by irqdomain because there may be multiple pins sharing the same IRQ number and current irqdomain only supports 1:1 mapping between pins and IRQ. Signed-off-by:
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Jiang Liu authored
Currently __acpi_register_gsi is defined to return GSI number and may be set to acpi_register_gsi_pic(), acpi_register_gsi_ioapic(), acpi_register_gsi_xen_hvm() and acpi_register_gsi_xen(). Among which, acpi_register_gsi_ioapic() returns GSI number, but acpi_register_gsi_xen_hvm() and acpi_register_gsi_xen() actually returns IRQ number instead of GSI. And for acpi_register_gsi_pic(), GSI number equals to IRQ number. So change acpi_register_gsi_ioapic() to return IRQ number, it also simplifies the code. Signed-off-by:
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Jiang Liu authored
Currently ACPI and ioapic both implement algorithms to map (ioapic, pin) to IRQ number. So consolidate the common part into one place, which is also preparing for irqdomain support. It introduces mp_map_gsi_to_irq(), which will be used to allocate IRQ number IOAPIC pins when irqdomain is enabled. Also rename gsi_to_irq() to map_gsi_to_irq(), later we will introduce unmap_gsi_to_irq() when enabling IOAPIC hotplug. Signed-off-by:
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Jiang Liu authored
Simplify function arch_early_irq_init() and kill static array irq_cfgx[]. Signed-off-by:
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Jiang Liu authored
Some platforms, such as Intel MID and mshypv, do not support legacy interrupt controllers. So count legacy IRQs by legacy_pic->nr_legacy_irqs instead of hard-coded NR_IRQS_LEGACY. Signed-off-by:
David Vrabel <david.vrabel@citrix.com> Link: http://lkml.kernel.org/r/1402302011-23642-20-git-send-email-jiang.liu@linux.intel.com Signed-off-by:
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Jiang Liu authored
Intel CE4100 platforms has i8259 legacy interrupt controllers, so don't set legacy_pic to null_legacy_pic in late booting stage because we need legacy_pic to mask i8259 pins when enabling IOAPIC pins for safety. Signed-off-by:
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Jiang Liu authored
Intel CE4100 platforms need IOAPIC support becasue some devices are always connected to the second IOAPIC, so make CONFIG_CE depends on CONFIG_X86_IO_APIC. Signed-off-by:
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Jiang Liu authored
It also fixes an off by one bug in if ((ioapic_idx > 0) && (irq > NR_IRQS_LEGACY)) It should be if ((ioapic_idx > 0) && (irq >= NR_IRQS_LEGACY)) Signed-off-by:
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Jiang Liu authored
Reorganize function IO_APIC_get_PCI_irq_vector() a bit to better support coming irqdomain. Signed-off-by:
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Jiang Liu authored
Use defined helper function irq_cfg() instead of irq_get_chip_data() for better readability. Signed-off-by:
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Jiang Liu authored
Introduce helper utilities for_each_ioapic(), for_each_ioapic_reverse(), for_each_pin() and for_each_ioapic_pin() to walk ioapics and pins. They will be rewritten e will rewrite later to support IOAPIC hotplug. Signed-off-by:
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