- Mar 09, 2022
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Bhupesh Sharma authored
Add the PCIe0 and PCIe1 GDSC defines & driver structures for SM8150. Cc: Stephen Boyd <sboyd@kernel.org> Cc: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by:
Bhupesh Sharma <bhupesh.sharma@linaro.org> Signed-off-by:
Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220302203045.184500-4-bhupesh.sharma@linaro.org
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Taniya Das authored
Support the new numerator and denominator for pixel clock on SM8350 and support rgb101010, RGB888 use cases on SM8450. Fixes: 99cbd064 ("clk: qcom: Support display RCG clocks") Signed-off-by:
Taniya Das <tdas@codeaurora.org> Reviewed-by:
Stephen Boyd <sboyd@kernel.org> Signed-off-by:
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Taniya Das authored
The display pixel clock has a requirement on certain newer platforms to support M/N as (2/3) and the final D value calculated results in underflow errors. As the current implementation does not check for D value is within the accepted range for a given M & N value. Update the logic to calculate the final D value based on the range. Fixes: 99cbd064 ("clk: qcom: Support display RCG clocks") Signed-off-by:
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Konrad Dybcio authored
Add missing RPM-provided clocks on msm8998 and reorder the definitions where needed. Tested-by:
Jami Kettunen <jami.kettunen@somainline.org> Signed-off-by:
Konrad Dybcio <konrad.dybcio@somainline.org> Tested-by:
Caleb Connolly <caleb@connolly.tech> Signed-off-by:
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Konrad Dybcio authored
XO and MSS_CFG were omitted when first adding the clocks for these SoCs. Add them, and while at it, move the XO clock to the top of the definition list, as ideally everyone should start using it sooner or later.. Fixes: b4297844 ("clk: qcom: smd: Add support for MSM8992/4 rpm clocks") Signed-off-by:
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Konrad Dybcio authored
Add the missing clock definitions. Signed-off-by:
Rob Herring <robh@kernel.org> Signed-off-by:
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Ansuel Smith authored
Add missing CryptoEngine resets. Signed-off-by:
Ansuel Smith <ansuelsmth@gmail.com> Reviewed-by:
Jonathan McDowell <noodles@earth.li> Signed-off-by:
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Ansuel Smith authored
Add ipq8064 ce5 resets needed for CryptoEngine gcc driver. Signed-off-by:
Philipp Zabel <p.zabel@pengutronix.de> Acked-by:
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Ansuel Smith authored
Add missing CryptoEngine clocks and pll11 required clock. Signed-off-by:
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Ansuel Smith authored
Add ipq8064 ce5 clk define needed for CryptoEngine in gcc driver. Define CE5_SRC is not used so it's OK to change and we align it to the QSDK naming. Signed-off-by:
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Ansuel Smith authored
Add additional freq supported for the sdc table. The ops are changed to the floor_ops to handle a freq request of 52kHz where we need to provide a freq of 51.2kHz instead for stability reason. Signed-off-by:
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Ansuel Smith authored
Add clk_rcg_floor_ops for clock that can't provide a stable freq and require to use a floor freq to provide the requested frequency. Signed-off-by:
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Ansuel Smith authored
Some clocks are used by other devices present on the SoC. For example the gsbi4_h_clk is used by RPM and is if disabled cause the RPM to reject any regulator change command. These clock should never be disabled. Signed-off-by:
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Ansuel Smith authored
Ipq8065 SoC (an evolution of ipq8064 SoC) contains nss cores that can be clocked to 800MHz. Add these missing freq to the gcc driver. Set the freq_tbl for the ubi32_cores to the correct values based on the machine compatible. Signed-off-by:
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Ansuel Smith authored
Use ARRAY_SIZE for num_parents instead of hardcoding the value. Signed-off-by:
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Ansuel Smith authored
Convert parent_names to parent_data to modernize the driver. Where possible use parent_hws directly. Signed-off-by:
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Ansuel Smith authored
Parent gcc_pxo_pll8_pll0 had the parent definition and parent map swapped. Fix this naming error. Signed-off-by:
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Ansuel Smith authored
Document qcom,gcc-ipq8064 binding needed to declare pxo and cxo source clocks. The gcc node is also used by the tsens driver, already documented, to get the calib nvmem cells and the base reg from gcc. Use qcom,gcc.yaml as a template and remove the compatible from generic qcom,gcc-other.yaml Signed-off-by:
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Ansuel Smith authored
Simplify qcon,gcc-apq8064 Documentation by using qcom,gcc.yaml as a template and remove the compatible from qcom,gcc.yaml Signed-off-by:
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Ansuel Smith authored
Split qcom,gcc.yaml to common and specific schema to use it as a template for schema that needs to use the gcc bindings and require to add additional bindings. Signed-off-by:
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Rohit Agarwal authored
Update APCS Kconfig to reflect support for SDX65 APCS clock controller. Signed-off-by:
Rohit Agarwal <quic_rohiagar@quicinc.com> Reviewed-by:
Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by:
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Rohit Agarwal authored
Update A7 PLL Kconfig to reflect support for SDX65. Signed-off-by:
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Rohit Agarwal authored
Add information for Cortex A7 PLL clock in Qualcomm platform SDX65. Signed-off-by:
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Konrad Dybcio authored
Add support for the GPU clock controller found on SM6350. Signed-off-by:
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Konrad Dybcio authored
Add device tree bindings for graphics clock controller for Qualcomm Technology Inc's SM6350 SoCs. Reviewed-by:
AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Signed-off-by:
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Konrad Dybcio authored
Add support for the display clock controller found on SM6350. Signed-off-by:
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Konrad Dybcio authored
Add device tree bindings for display clock controller for Qualcomm Technology Inc's SM6350 SoC. Signed-off-by:
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- Feb 25, 2022
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Bjorn Andersson authored
The Qualcomm SC8280XP platform exposes 5 clocks through the RPMh clock controller. Add these, and the relates active-only variants, to the RPMh clock controller driver. Signed-off-by:
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Bjorn Andersson authored
The Qualcomm SC8280XP has a RPMh clock controller, so add a compatible for this to the binding. Signed-off-by:
Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Link: https://lore.kernel.org/r/20220223044516.3776637-1-bjorn.andersson@linaro.org
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Dirk Buchwalder authored
Use floor ops on SDCC1 APPS clock in order to round down selected clock frequency and avoid overclocking SD/eMMC cards. For example, currently HS200 cards were failling tuning as they were actually being clocked at 384MHz instead of 192MHz. This caused some boards to disable 1.8V I/O and force the eMMC into the standard HS mode (50MHz) and that appeared to work despite the eMMC being overclocked to 96Mhz in that case. There was a previous commit to use floor ops on SDCC clocks, but it looks to have only covered SDCC2 clock. Fixes: 9607f622 ("clk: qcom: ipq8074: add PCIE, USB and SDCC clocks") Signed-off-by:
Dirk Buchwalder <buchwalder@posteo.de> Signed-off-by:
Robert Marko <robimarko@gmail.com> Reviewed-by:
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- Feb 24, 2022
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Dmitry Baryshkov authored
The driver can parse bi-tcxo clock from the clocks passed in the device tree. Specify it in schema. Signed-off-by:
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by:
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Dmitry Baryshkov authored
Convert clock/qcom,camcc.txt to clock/qcom,sdm845-camcc.yaml. Signed-off-by:
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- Feb 11, 2022
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Bartosz Dudziak authored
Modify the existing MSM8974 multimedia clock controller driver to support the MMCC found on MSM8226 based devices. This should allow most multimedia device drivers to probe and control their clocks. Signed-off-by:
Bartosz Dudziak <bartosz.dudziak@snejp.pl> Signed-off-by:
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Bartosz Dudziak authored
Document the multimedia clock controller found on MSM8226. Signed-off-by:
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Dmitry Baryshkov authored
The "xo" fixed_factor clock is a leftover/hack from a time when we couldn't make rpmhcc the root of all clocks. It is going to be removed once all users of this clock are converted to use clocks specified through the DTS. Replace internal usage of the xo clock with the cxo (RPM_SMD_BB_CLK1) parent, specifying xo_board as a fallback. Signed-off-by:
Marijn Suijten <marijn.suijten@somainline.org> Signed-off-by:
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Dmitry Baryshkov authored
Convert the clock driver to specify parent data rather than parent names, to actually bind using 'clock-names' specified in the DTS rather than global clock names. Use parent_hws where possible to refer parent clocks directly, skipping the lookup. Signed-off-by:
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Dmitry Baryshkov authored
Move clock parent tables down, after the GPLL declrataions, so that we can use gpll hw clock fields in the next commit. Signed-off-by:
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Dmitry Baryshkov authored
In preparation of updating the msm8996 gcc driver, drop all unsupported GPLL sources (gpll1/gpll1_early_div, gpll2/gpll2_early and gpll3). Downstream kernel also does not provide support for these GPLL sources, so it is safe to drop them. Signed-off-by:
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Dmitry Baryshkov authored
Use ARRAY_SIZE() instead of manually specifying num_parents. This makes adding/removing entries to/from parent_data easy and errorproof. Signed-off-by:
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Dmitry Baryshkov authored
If all parents are specified as clk_hw, we can use parent_hws instead of parent_data. Signed-off-by:
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