- Nov 24, 2009
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Becky Bruce authored
Code was added to mm/higmem.c that depends on several kmap types that powerpc does not support. We add dummy invalid definitions for KM_NMI, KM_NM_PTE, and KM_IRQ_PTE. According to list discussion, this fix should not be needed anymore starting with 2.6.33. The code is commented to this effect so hopefully we will remember to remove this. Signed-off-by:
Becky Bruce <beckyb@kernel.crashing.org> Signed-off-by:
Benjamin Herrenschmidt <benh@kernel.crashing.org>
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FUJITA Tomonori authored
We can kill unused swiotlb variable. Signed-off-by:
FUJITA Tomonori <fujita.tomonori@lab.ntt.co.jp> Signed-off-by:
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Stephen Rothwell authored
Since they are static inline functions. Signed-off-by:
Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by:
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Benjamin Herrenschmidt authored
The code under "if (is_global_init())" is bogus, and is_global_init() itself is not right in mt case. Contrary to what the comment says, nowadays force_sig_info() does kill init even if the handler is SIG_DFL. Note that force_sig_info() clears SIGNAL_UNKILLABLE exactly for this case. Signed-off-by:
Oleg Nesterov <oleg@redhat.com> Signed-off-by:
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Gautham R Shenoy authored
When a CPU is offlined on POWER currently, we call rtas_stop_self() and hand the CPU back to the resource pool. This path is used for DLPAR which will cause a change in the LPAR configuration which will be visible outside. This patch changes the default state a CPU is put into when it is offlined. On platforms which support ceding the processor to the hypervisor with latency hint specifier value, during a cpu offline operation, instead of calling rtas_stop_self(), we cede the vCPU to the hypervisor while passing a latency hint specifier value. The Hypervisor can use this hint to provide better energy savings. Also, during the offline operation, the control of the vCPU remains with the LPAR as oppposed to returning it to the resource pool. The patch achieves this by creating an infrastructure to set the preferred_offline_state() which can be either - CPU_STATE_OFFLINE: which is the current behaviour of calling rtas_stop_self() - CPU_STATE_INACTIVE: which cedes the vCPU to the hypervisor with the latency hint specifier. The codepath which wants to perform a DLPAR operation can set the preferred_offline_state() of a CPU to CPU_STATE_OFFLINE before invoking cpu_down(). The patch also provides a boot-time command line argument to disable/enable CPU_STATE_INACTIVE. Signed-off-by:
Gautham R Shenoy <ego@in.ibm.com> Signed-off-by:
Nathan Fontenot <nfont@austin.ibm.com> Signed-off-by:
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Gautham R Shenoy authored
This patch provides an extended_cede_processor() helper function which takes the cede latency hint as an argument. This hint is to be passed on to the hypervisor to cede to the corresponding state on platforms which support it. Signed-off-by:
Arun R Bharadwaj <arun@linux.vnet.ibm.com> Signed-off-by:
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Anton Blanchard authored
Move ehea hcall definitions into hvcall.h. Signed-off-by:
Anton Blanchard <anton@samba.org> Acked-by:
Thomas Klein <tklein@de.ibm.com> Signed-off-by:
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Thomas Gleixner authored
The typename member of struct irq_chip was kept for migration purposes and is obsolete since more than 2 years. Fix up the leftovers. Signed-off-by:
Thomas Gleixner <tglx@linutronix.de> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: linuxppc-dev@ozlabs.org Acked-by:
Geoff Levand <geoffrey.levand@am.sony.com> Signed-off-by:
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Thomas Gleixner authored
SPIN_LOCK_UNLOCKED is deprecated. Init the lock array at runtime instead. Signed-off-by:
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Thomas Gleixner authored
Drop the bkl from nvram_llseek() as it obviously protects nothing. The file offset is safe in essence. The ioctl can be converted to unlocked_ioctl because it just calls pmac_get_partition() which reads a value from an array which was initialized at early boot time. No need for serialization. Signed-off-by:
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Thomas Gleixner authored
The ioctl is only used for powermac systems and reads a partition number from an array which is initialized at boot time way before the nvram code is initialized. So it's safe to switch to unlocked_ioctl. Signed-off-by:
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roel kluin authored
size_t len cannot be less than 0. Signed-off-by:
Roel Kluin <roel.kluin@gmail.com> Acked-by:
Jeremy Kerr <jk@ozlabs.org> Signed-off-by:
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Benjamin Herrenschmidt authored
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- Nov 21, 2009
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Kumar Gala authored
Add basic support for the P4080 DS reference board. None of the data path devices (ethernet, crypto, pme) are support at this time. Signed-off-by:Kumar Gala <galak@kernel.crashing.org>
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Martyn Welch authored
Add support for NVRAM on GE Fanuc's PPC9A. Signed-off-by:
Martyn Welch <martyn.welch@gefanuc.com> Signed-off-by:
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Martyn Welch authored
Add support for NVRAM on GE Fanuc's SBC310. Signed-off-by:
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Martyn Welch authored
This patch enables the NVRAM found on the GE Fanuc SBC610 Signed-off-by:
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Kumar Gala authored
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Kumar Gala authored
Re-write the code so its more standalone and fixed some issues: * Bump'd # of CAM entries to 64 to support e500mc * Make the code handle MAS7 properly * Use pr_cont instead of creating a string as we go Signed-off-by: -
Kumar Gala authored
Introduce new FSL_SOC_BOOKE Kconfig to handle both 85xx and QorIQ based chips. Signed-off-by:
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- Nov 12, 2009
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Anton Vorontsov authored
Export is needed for modular builds, and a static inline stub is needed for non-MPC83xx builds. Signed-off-by:
Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by:
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Anton Vorontsov authored
Simply add power management controller nodes and sleep properties. Signed-off-by:
Scott Wood <scottwood@freescale.com> Signed-off-by:
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Anton Vorontsov authored
This patch adds needed nodes and properties to support suspend/resume on the MPC8610HPCD boards. There is a dedicated switch (SW9) that is used to wake up the boards. By default the SW9 button is routed to IRQ8, but could be re-routed (via PIXIS) to sreset. With 'no_console_suspend' kernel command line argument specified, the board is also able to wakeup upon serial port input. Signed-off-by:
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Anton Vorontsov authored
- Add power management controller nodes; - Add interrupts for RTC nodes, the RTC interrupt may be used as a wakeup source; - Add sleep properties (DEVDISR bit mask) and sleep-nexus nodes. Signed-off-by:
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Anton Vorontsov authored
This patch adds suspend/resume support for MPC8540 and MPC8641D- compatible CPUs. To reach sleep state, we just write the SLP bit into the PM control and status register. So far we don't support Deep Sleep mode as found in newer MPC85xx CPUs (i.e. MPC8536). It can be relatively easy implemented though, and for it we reserve 'mem' suspend type. Signed-off-by:
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Anton Vorontsov authored
So far the driver is used to reset QE upon resume, which is needed on 85xx. Later we can move some QE initialization steps into probe(). Signed-off-by:
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Anton Vorontsov authored
This patch adds QE buffer descriptors mode support for the spi_mpc8xxx driver, and as a side effect we now support CPM1 and CPM2 SPI controllers. That means that today we support almost all MPC SPI controllers: - MPC834x-style controllers (support PIO mode only); - CPM1 and CPM2 controllers (support DMA mode only); - QE SPI controllers in CPU mode (PIO mode with shift quirks); - QE SPI controllers in buffer descriptors (DMA) mode; The only controller we don't currently support is a newer eSPI (with a dedicated chip selects and a bit different registers map). Signed-off-by:
David Brownell <dbrownell@users.sourceforge.net> Signed-off-by:
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Anton Vorontsov authored
Soon there will be more flags introduced in subsequent patches, so let's turn qe_mode into flags. Also introduce mpc8xxx_spi_strmode() and print current SPI mode. Signed-off-by:
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Anton Vorontsov authored
We'll add more steps soon, so get rid of the duplication. Signed-off-by:
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Anton Vorontsov authored
This patch fixes the following warning: CC drivers/spi/spi_mpc8xxx.o spi_mpc8xxx.c: In function 'of_mpc8xxx_spi_probe': spi_mpc8xxx.c:681: warning: 'ret' may be used uninitialized in this function Signed-off-by:
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Anton Vorontsov authored
This is needed to avoid ugly #ifdefs in drivers. Also update fsl_qe_udc driver so that now it doesn't define its own versions that cause build breakage when the generic stubs are used. Signed-off-by:
Greg Kroah-Hartman <gregkh@suse.de> Signed-off-by:
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Anton Vorontsov authored
The bits are generic to CPM devices, so let's move them to the common header file, so drivers won't need to privately reintroduce another bunch of the same bits (as we can't include cpm2.h header together with cpm1.h). Signed-off-by:
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Anton Vorontsov authored
struct mcc defined in both immap_qe.h and immap_cpm2.h, so they will conflic when included in a single file. The mcc struct is easy to deal with, since it isn't used in any driver (yet), so let's just rename QE version to qe_mcc. The ucb_ctlr is a bit trickier, since it is used by fsl_qe_udc driver, and the driver supports both CPM and QE UDCs, plus the QE version is used to form a bigger immap struct. I don't want to touch too much of USB code in this series, so for now let's just copy most generic version into the common cpm.h header, later we'll create cpm_usb.h where we'll place common USB structs that are used by QE/CPM UDC and QE Host drivers (FHCI). And as for the structs in qe.h and cpm2.h, just prefix them with qe_ and cpm_. Signed-off-by:
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Anton Vorontsov authored
When cpm2.h included into spi_mpc8xxx driver, the SPI defines in the header conflict with defines in the driver. We don't need them in the header file, so remove them. Plus remove "struct spi", we'll use a better version in the driver. Signed-off-by:
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Poonam Aggrwal authored
P1020 is another member of Freescale QorIQ series of processors. It is an e500 based dual core SOC. Being a scaled down version of P2020 it has following differences from P2020: - 533MHz - 800MHz core frequency. - 256Kbyte L2 cache - Ethernet controllers with classification capabilities(new controller). From board perspective P1020RDB is same as P2020RDB. Signed-off-by:
Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by:
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Anton Vorontsov authored
It appears that QE shuts down on all MPC85xx CPUs (i.e. MPC8568 and MPC8569) and thus needs reset upon resume. So modify qe_alive_during_sleep() to account that. Signed-off-by:
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Anton Vorontsov authored
For MPC8569 CPUs we'll need to reset QE after each suspend, so make qe_reset() code path suitable for repeated invocation, that is: - Don't initialize rheap structures if already initialized; - Don't allocate muram for SDMA if already allocated, just reinitialize registers with previously allocated muram offset; - Remove __init attributes from qe_reset() and cpm_muram_init(); Signed-off-by:
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Poonam Aggrwal authored
This patch creates the dts files for each core and splits the devices between the two cores for P2020RDB. core0 has memory, L2, i2c, spi, dma1, usb, eth0, eth1, crypto, global-util, pci0, core1 has L2, dma2, eth0, pci1, msi. MPIC is shared between two cores but each core will protect its interrupts from other core by using "protected-sources" of mpic. Signed-off-by:
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Anton Vorontsov authored
This is needed to avoid #ifdefs in MPC85xx suspend/resume code. Signed-off-by:
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Anton Vorontsov authored
MPC8569 CPUs have four QE RISCs, so we need to increase MAX_QE_RISC constant, otherwise qe_upload_firmware() fails at sanity checking. Signed-off-by:
Timur Tabi <timur@freescale.com> Signed-off-by:
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