- Apr 01, 2015
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David Daney authored
Some hardware blocks attached to the OCTEON bootbus run asynchronously to accesses from the CPUs. These include MMC/SD host, CF(when using DMA), and NAND controller. A bus error, or corrupt data may occur if a CPU is trying to access a bootbus connected device at the same time the bus is running asynchronous operations. To work around these problems we add this semaphore that must be acquired before initiating bootbus activity. Subsequent patches will add users for this. Signed-off-by:
David Daney <david.daney@cavium.com> [aleksey.makarov@auriga.com: combine the patches] Signed-off-by:
Aleksey Makarov <aleksey.makarov@auriga.com> Signed-off-by:
Chandrakala Chavva <cchavva@caviumnetworks.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/9459/ Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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Kevin Cernekee authored
Most of the supported chips use legacy (non-DT) bootloaders, so they will need to select an appropriate builtin DTB at compile time until the bootloader is updated. Provide suitable DTS files, and a means to compile one of them into the kernel image. Signed-off-by:
Kevin Cernekee <cernekee@gmail.com> Signed-off-by:
Jaedon Shin <jaedon.shin@gmail.com> Cc: f.fainelli@gmail.com Cc: abrestic@chromium.org Cc: tglx@linutronix.de Cc: jason@lakedaemon.net Cc: jogo@openwrt.org Cc: arnd@arndb.de Cc: computersforpeace@gmail.com Cc: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/8858/ Signed-off-by:
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Kevin Cernekee authored
Add an entry for each supported Broadcom SoC. Signed-off-by:
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Kevin Cernekee authored
The DT bindings for this platform have changed as the bootloader and product requirements evolved. In particular, there are both Linux-on-Zephyr and Linux-on-Viper configurations. Signed-off-by:
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Kevin Cernekee authored
Also, add an LE defconfig for set-top box (BCM7xxx). This will allow the BMIPS kernel to run on several non-BCM3384 platforms. Signed-off-by:
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Kevin Cernekee authored
This will be required to support BMIPS3300 platforms. Signed-off-by:
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Kevin Cernekee authored
BCM3384/BCM63xx can use the common drivers/irqchip/irq-bcm7120-l2.c for this purpose; BCM7xxx will use drivers/irqchip/irq-bcm7038-l1.c. We no longer need this code under arch/mips. [ralf@linux-mips.org: Fix conflicts.] Signed-off-by:
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Kevin Cernekee authored
A couple of chips require special handling in order to make SMP secondary boot and/or exception vectors work correctly. Take care of these in setup.c. Signed-off-by:
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Kevin Cernekee authored
There is no "bcm3384" bus so let's just remove it to avoid confusion. Signed-off-by:
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Kevin Cernekee authored
This is a more standardized way of handling DMA remapping, and it is suitable for the memory map found on BCM3384. Signed-off-by:
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Kevin Cernekee authored
Add a new section covering the Generic BMIPS machine type. Signed-off-by:
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Kevin Cernekee authored
Enabling support for more than one BMIPS CPU in the same build may result in different L1_CACHE_SHIFT values, e.g. CPU_BMIPS5000 selects MIPS_L1_CACHE_SHIFT_7 CPU_BMIPS4380 selects MIPS_L1_CACHE_SHIFT_6 anything else defaults to MIPS_L1_CACHE_SHIFT_5 Ensure that if more than one MIPS_L1_CACHE_SHIFT_x option is selected, Kconfig sets CONFIG_MIPS_L1_CACHE_SHIFT to the highest value. Signed-off-by: -
Kevin Cernekee authored
Some machines only have one bus type to register (e.g. "simple-bus"). Signed-off-by:
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Kevin Cernekee authored
This is the main peripheral IRQ controller on the BCM7xxx MIPS chips; it has the following characteristics: - 64 to 160+ level IRQs - Atomic set/clear registers - Reasonably predictable register layout (N status words, then N mask status words, then N mask set words, then N mask clear words) - SMP affinity supported on most systems - Typically connected to MIPS IRQ 2,3,2,3 on CPUs 0,1,2,3 This driver registers one IRQ domain and one IRQ chip to cover all instances of the block. Up to 4 instances of the block may appear, as it supports 4-way IRQ affinity on BCM7435. The same block exists on the ARM BCM7xxx chips, but typically the ARM GIC is used instead. So this driver is primarily intended for MIPS STB chips. Signed-off-by:
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Kevin Cernekee authored
These controllers support multiple enable/status pairs (64+ IRQs), can put the enable/status words at different offsets, and do not support multiple parent IRQs. Signed-off-by:
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Kevin Cernekee authored
The BCM7xxx instances of this block (listed in the register manual as simply "IRQ0") all have the following items in common: - brcm,int-map-mask: for routing different bits in the L2 to different parent IRQs - brcm,int-fwd-mask: for hardwiring certain IRQs to bypass the L2 and use dedicated L1 lines - one enable/status pair (32 bits only) Much of the driver code can be shared with BCM3380-style controllers, but in order to do this cleanly, let's split out the BCM7xxx-specific logic first. Signed-off-by:
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Kevin Cernekee authored
Currently the driver assumes that REG_BASE+0x00 is the IRQ enable mask, and REG_BASE+0x04 is the IRQ status mask. This is true on BCM3384 and BCM7xxx, but it is not true for some of the controllers found on BCM63xx chips. So we will change a couple of key assumptions: - Don't assume that both the IRQEN and IRQSTAT registers will be covered by a single ioremap() operation. - Don't assume any particular ordering (IRQSTAT might show up before IRQEN on some chips). - For an L2 controller with >=64 IRQs, don't assume that every IRQEN/IRQSTAT pair will use the same register spacing. This patch changes the "plumbing" but doesn't yet provide a way for users to instantiate a controller with arbitrary IRQEN/IRQSTAT offsets. Signed-off-by:
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Brian Norris authored
Wakeable interrupts might be pending at boot/init time, because wakeup interrupts might have triggered a resume from S5. So don't clear such wakeups. This means that any driver which requests a wakeable interrupt bit should be prepared to handle an interrupt as soon as they call request_irq(). (This is technically already the correct development practice, but some drivers probably expect not to receive interrupts until they have performed some I/O.) Signed-off-by:
Brian Norris <computersforpeace@gmail.com> Signed-off-by:
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Kevin Cernekee authored
Several drivers now use this API, including the ARM GIC driver, so remove the outdated comment. Signed-off-by:
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Kevin Cernekee authored
This platform is configured primarily through device tree, and we can reuse the same code to support a bunch of other chips. Change the name to reflect this. [ralf@linux-mips.org: Fix conflicts with other patches.] Signed-off-by:
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Andrew Bresticker authored
Add the dtbs_install Makefile target to install the dtb files into $INSTALL_DTBS_PATH. Signed-off-by:
Andrew Bresticker <abrestic@chromium.org> Tested-by:
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Andrew Bresticker authored
Move the MIPS device-trees into the appropriate vendor sub-directories. Signed-off-by:
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Deng-Cheng Zhu authored
With sched_clock being ready, it makes sense to add the option of IRQ time accounting -- When we have a fast enough sched_clock, IRQ time accounting will be enabled (see sched_clock_register). Signed-off-by:
Deng-Cheng Zhu <dengcheng.zhu@imgtec.com> Cc: linux-mips@linux-mips.org Cc: macro@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9489/ Signed-off-by:
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Deng-Cheng Zhu authored
Use sb1250 hpt for sched_clock source. This implementation will give high resolution cputime accounting. Signed-off-by:
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Deng-Cheng Zhu authored
This is to make checkpatch.pl happy for the next patch. It would otherwise say -- ERROR: Do not include the paragraph about writing to the Free Software Foundation's mailing address from the sample GPL notice. The FSF has changed addresses in the past, and may do so again. Linux already includes a copy of the GPL. Signed-off-by:
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Deng-Cheng Zhu authored
This is to prepare for the upcoming read_sched_clock implementation, which will also need to get cycles from the high precision timer. Signed-off-by:
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Deng-Cheng Zhu authored
Use jz4740 timer counter for sched_clock source. This implementation will give high resolution cputime accounting. Signed-off-by:
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Deng-Cheng Zhu authored
Use txx9 up-counter for sched_clock source. This implementation will give high resolution cputime accounting. Signed-off-by:
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Deng-Cheng Zhu authored
Use ip27 hub real time counter for sched_clock source. This implementation will give high resolution cputime accounting. Signed-off-by:
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Deng-Cheng Zhu authored
Use DEC I/O ASIC's free-running counter for sched_clock source. This implementation will give high resolution cputime accounting. Acked-by:
Maciej W. Rozycki <macro@linux-mips.org> Signed-off-by:
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Deng-Cheng Zhu authored
This is to make checkpatch.pl happy for the next patch. It would otherwise say -- ERROR: Do not include the paragraph about writing to the Free Software Foundation's mailing address from the sample GPL notice. The FSF has changed addresses in the past, and may do so again. Linux already includes a copy of the GPL. Acked-by:
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Deng-Cheng Zhu authored
Use the ZBbus cycle counter for sched_clock source. This implementation will give high resolution cputime accounting. Signed-off-by:
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Deng-Cheng Zhu authored
This is to make checkpatch.pl happy for the next patch. It would otherwise say -- ERROR: Do not include the paragraph about writing to the Free Software Foundation's mailing address from the sample GPL notice. The FSF has changed addresses in the past, and may do so again. Linux already includes a copy of the GPL. Signed-off-by:
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Deng-Cheng Zhu authored
Use c0 count register for sched_clock source. This implementation will give high resolution cputime accounting. Signed-off-by:
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Deng-Cheng Zhu authored
This will provide sched_clock interface to implement individual read_sched_clock(). Not for CAVIUM_OCTEON_SOC as it defines its own sched_clock() directly (not using the sched_clock_register interface). Signed-off-by:
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Deng-Cheng Zhu authored
GENERIC_SCHED_CLOCK can be selected by architectures other than ARM. The current dependencies of CLKSRC_VERSATILE make it possible that other architectures will have CLKSRC_VERSATILE available in configuration once they select GENERIC_SCHED_CLOCK, whereas this clock source should be solely available to ARM in reality. This patch adds one more dependency to CLKSRC_VERSATILE to fix the issue. Signed-off-by:
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Deng-Cheng Zhu authored
With the correct cmpxchg64 on 32-bit platforms, we can now add the config HAVE_VIRT_CPU_ACCOUNTING_GEN into arch/mips/Kconfig. Signed-off-by:
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Deng-Cheng Zhu authored
This is in preparation of adding HAVE_VIRT_CPU_ACCOUNTING_GEN support in the next patch. Without having cmpxchg64 to use the generic implementation, kernel linking will complain: kernel/built-in.o: In function `cputime_adjust': cputime.c:(.text+0x33748): undefined reference to `__cmpxchg_called_with_bad_pointer' cputime.c:(.text+0x33810): undefined reference to `__cmpxchg_called_with_bad_pointer' Signed-off-by:
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Deng-Cheng Zhu authored
We have HIGH_RES_TIMERS to support SCHED_HRTICK. But SCHED_HRTICK is in kernel/Kconfig.hz where HZ values unsuitable for MIPS are defined. So we simply add this config in arch/mips/Kconfig as opposed to including the whole kernel/Kconfig.hz. Signed-off-by:
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David Daney authored
Now it is supported, so let people select it. [ralf@linux-mips.org: Folded in fix for bogus CONFIG_ kconfig symbol prefix. Issue reported by Valentin Rothberg <valentinrothberg@gmail.com>.] Signed-off-by:
Leonid Rosenboim <lrosenboim@caviumnetworks.com> Signed-off-by:
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