- Aug 16, 2023
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Mario Limonciello authored
DCN 3.1.4 is reported to hang on s2idle entry if graphics activity is happening during entry. This is because GFXOFF was scheduled as delayed but RLC gets disabled in s2idle entry sequence which will hang GFX IP if not already in GFXOFF. To help this problem, flush any delayed work for GFXOFF early in s2idle entry sequence to ensure that it's off when RLC is changed. commit 4b31b92b ("drm/amdgpu: complete gfxoff allow signal during suspend without delay") modified power gating flow so that if called in s0ix that it ensured that GFXOFF wasn't put in work queue but instead processed immediately. This is dead code due to commit 10cb67eb ("drm/amdgpu: skip CG/PG for gfx during S0ix") because GFXOFF will now not be explicitly called as part of the suspend entry code. Remove that dead code. Signed-off-by:
Mario Limonciello <mario.limonciello@amd.com> Signed-off-by:
Tim Huang <tim.huang@amd.com> Reviewed-by:
Lijo Lazar <lijo.lazar@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Tim Huang authored
GFX v11.0.1 reported fence fallback timer expired issue on SDMA and GFX rings after S0ix resume. This is generated by EOP interrupts are disabled when S0ix suspend but fails to re-enable when resume because of the GFX is in GFXOFF. [ 203.349571] [drm] Fence fallback timer expired on ring sdma0 [ 203.349572] [drm] Fence fallback timer expired on ring gfx_0.0.0 [ 203.861635] [drm] Fence fallback timer expired on ring gfx_0.0.0 For S0ix, GFX is in GFXOFF state, avoid to touch the GFX registers to configure the fence driver interrupts for rings that belong to GFX. The interrupts configuration will be restored by GFXOFF exit. Signed-off-by:
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Lijo Lazar authored
GFXOFF feature is not there for GFX 9.4.3 ASICs. Signed-off-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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Asad Kamal authored
Update pcie link speed registers for smu v13.0.6 & populate gpu metric table with pcie link speed rather than gen for smu v13_0_0, smu v13_0_6 & smu v13_0_7 v2: Update ESM register address Used macro to convert pcie gen to speed v3: Chaged macro to inline function for pcie gen to speed Signed-off-by:
Asad Kamal <asad.kamal@amd.com> Reviewed-by:
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Kenneth Feng authored
allow the user to force BACO on smu v13.0.0/7 Signed-off-by:
Kenneth Feng <kenneth.feng@amd.com> Acked-by:
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James Zhu authored
Return 0 when drm device alloc failed with -ENOSPC in order to allow amdgpu drive loading. But the xcp without drm device node assigned won't be visiable in user space. This helps amdgpu driver loading on system which has more than 64 nodes, the current limitation. The proposal to add more drm nodes is discussed in public, which will support up to 2^20 nodes totally. kernel drm: https://lore.kernel.org/lkml/20230724211428.3831636-1-michal.winiarski@intel.com/T/ libdrm: https://gitlab.freedesktop.org/mesa/drm/-/merge_requests/305 Signed-off-by:
James Zhu <James.Zhu@amd.com> Acked-by:
Christian König <christian.koenig@amd.com> Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
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Asad Kamal authored
Update addresses of PCIE link width registers, & link width format used to populate gpu metrics table for smu v13.0.6 v2: Removed ESM register update v3: Updated patch subject and message Signed-off-by:
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Samir Dhume authored
CG/PG is handled on the host side. Signed-off-by:
Samir Dhume <samir.dhume@amd.com> Acked-by:
Leo Liu <leo.liu@amd.com> Signed-off-by:
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Bhawanpreet Lakha authored
Handle replay related hpd irqs Signed-off-by:
Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
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Samir Dhume authored
initialization table handshake with mmsch Signed-off-by:
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Bhawanpreet Lakha authored
Update infopackets for replay Signed-off-by:
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Aric Cyr authored
This version brings along following fixes: - Improve power saving feature - Clean up for code clarity - Fix crashing bug - Fix pipe allocation for older ASIC - Fix for gamut remap - Fix 8K 60Hz display in test cases - Fix bug in clock gating - Improve DP2 compliance Acked-by:
Stylon Wang <stylon.wang@amd.com> Signed-off-by:
Aric Cyr <aric.cyr@amd.com> Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
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Anthony Koo authored
- Add defines to specify new PHY power states Acked-by:
Anthony Koo <anthony.koo@amd.com> Tested-by:
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Srinivasan Shanmugam authored
Fixes the following coccicheck: drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c:2482:16-17: WARNING opportunity for min() min() macro is defined in include/linux/minmax.h. It avoids multiple evaluations of the arguments when non-constant and performs strict type-checking. Cc: Guchun Chen <guchun.chen@amd.com> Cc: Christian König <christian.koenig@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: "Pan, Xinhui" <Xinhui.Pan@amd.com> Signed-off-by:
Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> Reviewed-by:
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Srinivasan Shanmugam authored
Fixes the following coccicheck: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c:120:41-42: WARNING opportunity for min() Cc: Harry Wentland <harry.wentland@amd.com> Cc: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Cc: Aurabindo Pillai <aurabindo.pillai@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by:
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Mario Limonciello authored
Some ASICS only offer one type of power attribute, so in the visible callback check whether the attributes are supported and hide if not supported. Signed-off-by:
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Mario Limonciello authored
Use the clearer name `AMDGPU_PP_SENSOR_GPU_AVG_POWER` instead. Signed-off-by:
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Mario Limonciello authored
Vega20 can offer average power in some versions of the PMFW and current power in others. Signed-off-by:
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Mario Limonciello authored
Aldebaran can only return average socket power for the first die. The other dies return 0. Instead of returning a bad value, return -EOPNOTSUPP so that the attribute will be hidden. Signed-off-by:
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Mario Limonciello authored
aldebaran_get_gpu_power() is only called by one place and just calls aldebaran_get_smu_metrics_data(), so drop the helper. Signed-off-by:
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Mario Limonciello authored
The average power for the GPU metrics sysfs file contains the input power not the average power. The member that is set is called average power though, so correct it to the right value. Signed-off-by:
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Zheng Zengkai authored
PCI core API pci_dev_id() can be used to get the BDF number for a pci device. We don't need to compose it mannually. Use pci_dev_id() to simplify the code a little bit. Signed-off-by:
Zheng Zengkai <zhengzengkai@huawei.com> Signed-off-by:
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GUO Zihua authored
Remove duplicated includes in amdgpu_amdkfd_gpuvm.c and amdgpu_ttm.c. Resolves checkincludes message. Signed-off-by:
GUO Zihua <guozihua@huawei.com> Signed-off-by:
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Ran Sun authored
Fix the following errors reported by checkpatch: ERROR: open brace '{' following enum go on the same line ERROR: open brace '{' following struct go on the same line Signed-off-by:Ran Sun <sunran001@208suo.com> Signed-off-by:
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Aurabindo Pillai authored
[Why] When unused, all memory blocks should be put in a low power state [How] Check the value of enable_mem_low_power.bits.vga and set corresponding bit in the hardware register Acked-by:
Aurabindo Pillai <aurabindo.pillai@amd.com> Reviewed-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Tested-by:
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Ran Sun authored
Fix the following errors reported by checkpatch: ERROR: trailing whitespace ERROR: open brace '{' following struct go on the same line ERROR: code indent should use tabs where possible Signed-off-by: -
Alex Deucher authored
Allow the user to specify -2 as auto enabled with displays. By default we don't enter runtime suspend when there are displays attached because it does not work well in some desktop environments due to the driver sending hotplug events on resume in case any new displays were attached while the GPU was powered down. Some users still want this functionality though, so this lets you enable it. Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2428 Reviewed-by:
Guchun Chen <guchun.chen@amd.com> Signed-off-by:
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Mario Limonciello authored
Some GPUs have been overloading average power values and input power values. To disambiguate these, introduce a new `AMDGPU_PP_SENSOR_GPU_INPUT_POWER` and the GPUs that share input power update to use this instead of average power. Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2746 Signed-off-by:
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Aurabindo Pillai authored
[Why&How] Freesync Video mode was enabled by default. Hence no need for the module parameter, so remove it completely Acked-by:
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Mario Limonciello authored
Some GPUs provide support for current power, some average power, and some both. To be able to support all these combinations, introduce a new attribute. Signed-off-by:
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Samir Dhume authored
initialization table handshake with mmsch Signed-off-by:
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Srinivasan Shanmugam authored
Fixes the following coccicheck: drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c:2427:16-17: WARNING opportunity for min() min() macro is defined in include/linux/minmax.h. It avoids multiple evaluations of the arguments when non-constant and performs strict type-checking. Cc: Guchun Chen <guchun.chen@amd.com> Cc: Christian König <christian.koenig@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: "Pan, Xinhui" <Xinhui.Pan@amd.com> Signed-off-by:
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Aurabindo Pillai authored
[Why&How] Add some missing register definitions and rearrange some others to maintain consistency with related definitions. Acked-by:
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Charlene Liu authored
[why] add dml1 used calculate_wm_and_dlg function pointer check to prevent crash. add z8 watermarks to struct for later asic use Reviewed-by:
Alvin Lee <alvin.lee2@amd.com> Acked-by:
Charlene Liu <charlene.liu@amd.com> Tested-by:
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Wenjing Liu authored
[why] There is a lack of encapsulation of pipe connection representation in pipe context. This has caused many challenging bugs and coding errors with repeated logic to identify the same pipe type. [how] Formally define pipe types and provide getters to identify a pipe type and find a pipe based on specific requirements. Update existing logic in non dcn specific files and dcn32 and future versions to use the new accessors. Reviewed-by:
Jun Lei <jun.lei@amd.com> Acked-by:
Wenjing Liu <wenjing.liu@amd.com> Tested-by:
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Nicholas Susanto authored
[Why] 8k60hz compliace test failing because we restrict it single memory channels. Workaround by not restricting it on single displays. [How] Adding an additional check to DCN314 to restrict 8k60hz mode if it has more than 1 display connected. Reviewed-by:
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Acked-by:
Nicholas Susanto <nicholas.susanto@amd.com> Signed-off-by:
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Wenjing Liu authored
[why] There is a recent work for developing a new pipe resource allocation policy used for new ASIC. The new code change needs to modify asic independent pipe resource allocation flow and hook up the new allocation policy in asic dependent layer. Unfortunately this change revealed a hidden bug in the old pipe resource allocation sequence used for older asics. In the older version of acquiring pipe for layer, we are always assigning otg master's opp and tg to the newly allocated secondary dpp pipe. This logic is incorrect when the secodnary dpp pipe is connected to a secondary opp head pipe in ODM combine configuration. Before the recent change, we will overwrite this wrong assignement in asic independent layer again. This covers up the issue. With the recent change, we will no longer cover up this in upper layer and therefore causes wrong tg and opp assignement to the secondary dpp pipe connected to a secondary opp head. [how] Always assign tg and opp from its own opp head instead of otg master. Reviewed-by:
Martin Leung <martin.leung@amd.com> Acked-by:
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Krunoslav Kovac authored
[WHY&HOW] If surface format is dynamically changed within app without changing timing / whole plane, we don't reprogram gamut remap matrix. Issue example: Linear FP16 scRGB going to PQ+BT.2020 monitor. Remap = scRGB->BT.2020 App switches swapchain format to 10-bit PQ+BT.2020. SW calculates correctly that new Remap = bypass (in=-out=BT.2020). But update not applied in HW. Reviewed-by:
Krunoslav Kovac <krunoslav.kovac@amd.com> Tested-by:
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Alvin Lee authored
[Description] We want PMFW to wait for DMCUB to ACK the MCLK end message for FPO cases as well. Reviewed-by:
Samson Tam <samson.tam@amd.com> Acked-by:
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Alvin Lee authored
[Description] Expand the SubVP policy to include up to 175hz displays for better power saving on more display configs. Reviewed-by:
Chaitanya Dhere <chaitanya.dhere@amd.com> Acked-by:
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