- Jul 15, 2022
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Chunfeng Yun authored
Add compatible for mt8188 Signed-off-by:
Chunfeng Yun <chunfeng.yun@mediatek.com> Acked-by:
Rob Herring <robh@kernel.org> Reviewed-by:
Matthias Brugger <matthias.bgg@gmail.com> Link: https://lore.kernel.org/r/20220708065834.25424-1-chunfeng.yun@mediatek.com Signed-off-by:
Vinod Koul <vkoul@kernel.org>
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Samuel Holland authored
When the OTG port is fixed to host mode, the driver does not request its IRQs, nor does it enable those IRQs in hardware. Similarly, the driver should ignore the OTG port IRQs when handling the shared interrupt. Otherwise, it would update the extcon based on an ID pin which may be in an undefined state, or try to queue a uninitialized work item. Fixes: 6a98df08 ("phy: rockchip-inno-usb2: Fix muxed interrupt support") Reported-by:
Frank Wunderlich <frank-w@public-files.de> Signed-off-by:
Samuel Holland <samuel@sholland.org> Tested-by:
Peter Geis <pgwipeout@gmail.com> Tested-by:
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Vinod Koul authored
qmp_phy_vreg_l should be marked static, this resolves warning: drivers/phy/qualcomm/phy-qcom-qmp-combo.c:616:27: warning: symbol 'qmp_phy_vreg_l' was not declared. Should it be static? Signed-off-by:
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Fabrice Gasnier authored
Error code is overridden, in case the PLL doesn't lock. So, the USB initialization can continue. This leads to a platform freeze. This can be avoided by returning proper error code to avoid USB probe freezing the platform. It also displays proper errors in log. Fixes: 5b1af712 ("phy: stm32: rework PLL Lock detection") Signed-off-by:
Fabrice Gasnier <fabrice.gasnier@foss.st.com> Link: https://lore.kernel.org/r/20220713133953.595134-1-fabrice.gasnier@foss.st.com Signed-off-by:
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- Jul 08, 2022
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Yang Yingliang authored
mtk_dp_phy_driver is only used in phy-mtk-dp.c now, change it to static. Signed-off-by:
Yang Yingliang <yangyingliang@huawei.com> Link: https://lore.kernel.org/r/20220707135309.801181-1-yangyingliang@huawei.com Signed-off-by:
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Liu Ying authored
Add Freescale i.MX8qm LVDS PHY support. The PHY IP is from Mixel, Inc. Signed-off-by:
Liu Ying <victor.liu@nxp.com> Link: https://lore.kernel.org/r/20220706034810.2352641-4-victor.liu@nxp.com Signed-off-by:
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Liu Ying authored
Add bindings for Mixel LVDS PHY found on Freescale i.MX8qm SoC. Reviewed-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by:
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Liu Ying authored
Add a vendor prefix entry for Mixel, Inc. (https://www.mixel.com ). Acked-by:
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Lars-Peter Clausen authored
The driver state struct for the sierra PHY driver has a field named `regmap` that is never referenced. Remove it since it is unused. Not that there are separate fields of type `struct regmap` for the individual sections of the device's register map. These other regmaps are used and not affected by the patch. Signed-off-by:
Lars-Peter Clausen <lars@metafoo.de> Link: https://lore.kernel.org/r/20220707071722.44201-2-lars@metafoo.de Signed-off-by:
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Lars-Peter Clausen authored
The driver state struct for the sierra PHY driver has a field named `regmap` that is never referenced. Remove it since it is unused. Not that there are separate fields of type `struct regmap` for the individual sections of the device's register map. These other regmaps are used and not affected by the patch. Signed-off-by:
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Chanho Park authored
The sequence of controlling ufs phy block should be below: 1) Power On - Turn off pmu isolation - Clock enable 2) Power Off - Clock disable - Turn on pmu isolation Signed-off-by:
Chanho Park <chanho61.park@samsung.com> Reviewed-by:
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Chanho Park authored
Instead of using separated clock manipulation, this converts the phy clock usage to be clk_bulk APIs. By using this, we can completely remove has_symbol_clk check and symbol clk variables. Furthermore, clk_get should be moved to probe because there is no need to get them in the phy_init callback. Signed-off-by:
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- Jul 07, 2022
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Dmitry Baryshkov authored
Other PHYs tables directly reference QPHY_PLL_LOCK_CHK_DLY_TIME register without using reglayout. Define corresponding register to be used by msm8996 PHY tables and use it directly. Signed-off-by:
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20220705094320.1313312-29-dmitry.baryshkov@linaro.org Signed-off-by:
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Dmitry Baryshkov authored
Other PHYs tables directly reference FLL registers without using reglayout. Define corresponding registers to be used by msm8996 PHY tables and use them directly. Signed-off-by:
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Dmitry Baryshkov authored
Add missing registers, verified against: - msm-4.19's qcom,kona-qmp-usb3.h Signed-off-by:
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Dmitry Baryshkov authored
Add missing registers, verified against: - msm-4.19's qcom,usb3-11nm-qmp-combo.h Signed-off-by:
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Dmitry Baryshkov authored
Add missing registers, verified against: - msm-5.4's qcom,usb3-5nm-qmp-uni.h - msm-5.4's qcom,usb3-5nm-qmp-combo.h Signed-off-by:
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Dmitry Baryshkov authored
Add missing registers, verified against: - msm-4.19's qcom,kona-qmp-usb3.h The 0x1a0 register name was corrected, verified via msm-4.14's qcom,sdxprairie-qmp-usb3.h. Signed-off-by:
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Dmitry Baryshkov authored
Add missing registers, verified against: - msm-4.4's phy-qcom-ufs-qmp-v3.h Signed-off-by:
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Dmitry Baryshkov authored
Add missing registers, verified against: - msm-3.18's phy-qcom-ufs-qmp-14nm.h - msm-3.18's mdss-hdmi-pll-8996.c - msm-5.4's ep_pcie_phy.h Signed-off-by:
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Dmitry Baryshkov authored
Several registers defined in the PCS V3 namespace in reality belong to the PCS_UFS V3 register space. Move them to the separate header and rename them to explicitly mention PCS_UFS. While we are at it, correct one register in the msm8998_usb3_pcs_tbl table to use PCS register name. Signed-off-by:
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Dmitry Baryshkov authored
Split registers definitions belonging allegedly to 4.20 and 5.20 QMP PHYs. They are used for the PCIe QMP PHYs, which have no good open source reference. Signed-off-by:
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Dmitry Baryshkov authored
Split registers definitions belonging allegedly to 4.20 and 5.20 QMP PHYs. They are used for the PCIe QMP PHYs, which have no good open source reference. Signed-off-by:
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Dmitry Baryshkov authored
Move PCIE QHP registers to the separate header. QHP is a sepecial PHY kind used on sdm845 to drive one of PCIe links. Signed-off-by:
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Dmitry Baryshkov authored
Move PCS V5 registers to the separate headers. Signed-off-by:
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Dmitry Baryshkov authored
Move PCS V4 registers to the separate headers. Signed-off-by:
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Dmitry Baryshkov authored
Move PCS V3 registers to the separate headers. Signed-off-by:
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Dmitry Baryshkov authored
Move PCS V2 registers to the separate header. Signed-off-by:
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Dmitry Baryshkov authored
Move QSERDES PLL registers to the separate header. This register set is unique for the IPQ PCIe Gen3 PHYs. Signed-off-by:
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Dmitry Baryshkov authored
Move QSERDES V5 registers to the separate headers. Signed-off-by:
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Dmitry Baryshkov authored
Move QSERDES V4 registers to the separate headers. Signed-off-by:
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Dmitry Baryshkov authored
Move QSERDES V3 registers to the separate headers. Signed-off-by:
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Dmitry Baryshkov authored
Move QSERDES V2 registers to the separate header. Signed-off-by:
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Dmitry Baryshkov authored
PCS_COM_* symbols duplicate the QPHY_V4_PCS_*. PCS_PCIE_* symbols duplicate the QPHY_V4_PCS_PCIE_*. Use generic register names for the IPQ6018 and IPQ8074 tables and drop the custom PCS_COM_*/PCS_PCIE* names. Signed-off-by:
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Dmitry Baryshkov authored
Rename QMP V2 PCS registers to follow the usual pattern of QPHY_V2_PCS_*. Signed-off-by:
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Dmitry Baryshkov authored
Replace separate defines for QMP V2 PHY for PCIe gen3 ports. They are equivalent to the QSERDES_V4_ symbols. Signed-off-by:
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Dmitry Baryshkov authored
Follow the example of other PCIe PHYs and use separate pcs_misc region to access PCS_PCIE_* resources. Signed-off-by:
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Dmitry Baryshkov authored
Different QMP USB PHYs might have different offset from PCS to PCS_USB register space, but the same PCS_USB register layout. Add separate PCS_USB region space and merge related PCS_USB definitions. Signed-off-by:
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Dmitry Baryshkov authored
The msm8996_ufs_serdes_tbl table contains write to QPHY_POWER_DOWN_CONTROL, however this register doesn't belong to the QSERDES register space. Also the PHY power down is already handled in the qcom_qmp_phy_ufs_com_init(). Drop this entry completely. Signed-off-by:
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Dmitry Baryshkov authored
Change QSERDES_V5_COM_CMN_MODE to be defined to 0x1a0 rather than 0x1a4. The only user of this register name (sm8450_qmp_gen4x2_pcie_serdes_tbl) should use the 0x1a0 register, as stated in the downstream dtsi tree. Fixes: 2c91bf6b ("phy: qcom-qmp: Add SM8450 PCIe1 PHY support") Signed-off-by:
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