- Aug 14, 2023
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Imran Shaik authored
gcc_gpll1_out_even clock is referenced as a parent, but not registered with the clock framework. Hence add support to register the same. Fixes: 1c9efb0b ("clk: qcom: Add QDU1000 and QRU1000 GCC support") Signed-off-by:
Imran Shaik <quic_imrashai@quicinc.com> Reviewed-by:
Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20230803105741.2292309-5-quic_imrashai@quicinc.com Signed-off-by:
Bjorn Andersson <andersson@kernel.org>
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Imran Shaik authored
Update the GCC clkref clock's halt_check to BRANCH_HALT, as it's status bit is not inverted in the latest hardware version of QDU1000 and QRU1000 SoCs. While at it, fix the gcc clkref clock ops as well. Fixes: 1c9efb0b ("clk: qcom: Add QDU1000 and QRU1000 GCC support") Signed-off-by:
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Imran Shaik authored
Fix the gcc pcie pipe clock handling as per the clk_regmap_phy_mux_ops implementation to let the clock framework automatically park the clock at XO when the clock is switched off and restore the parent when the clock is switched on. Fixes: 1c9efb0b ("clk: qcom: Add QDU1000 and QRU1000 GCC support") Co-developed-by:
Taniya Das <quic_tdas@quicinc.com> Signed-off-by:
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Imran Shaik authored
Add support for GCC_GPLL1_OUT_EVEN and GCC_DDRSS_ECPRI_GSI_CLK clock bindings for QDU1000 and QRU1000 SoCs. While at it, update the maintainers list. Signed-off-by:
Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20230803105741.2292309-2-quic_imrashai@quicinc.com Signed-off-by:
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Konrad Dybcio authored
Use the floor ops to prevent warnings like this at suspend exit and boot: mmc0: Card appears overclocked; req 800000 Hz, actual 25000000 Hz Fixes: db0c944e ("clk: qcom: Add clock driver for SM8450") Signed-off-by:
Vinod Koul <vkoul@kernel.org> Link: https://lore.kernel.org/r/20230811-topic-8450_clk-v1-1-88031478d548@linaro.org Signed-off-by:
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Kathiravan T authored
With the removal of the mem noc clocks in the commit e224dc703521 ("clk: qcom: gcc-ipq5332: drop the mem noc clocks"), we can drop the gcc_apss_axi_clk_src clock as well, since there are no clocks uses this clock as a parent. Signed-off-by:Kathiravan T <quic_kathirav@quicinc.com> Link: https://lore.kernel.org/r/20230710102807.1189942-3-quic_kathirav@quicinc.com Signed-off-by:
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Kathiravan T authored
Due to the recent design changes, all the mem noc clocks will be configured by the bootloaders and it will be access protected by the TZ firmware. So drop these clocks from the GCC driver. Signed-off-by:
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Konrad Dybcio authored
Some branch clocks are governed externally and we're only supposed to send a request concerning their shutdown, not actually ensure it happens. Use the BRANCH_HALT_SKIP define to skip checking the halt bit. Reviewed-by:
Jeffrey Hugo <quic_jhugo@quicinc.com> Signed-off-by:
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Konrad Dybcio authored
GPUCC has its own GPLL0 legs - one for 1-1 and one for div-2 output. Add .name lookup to make sure older DTs consume the correct clock. Reviewed-by:
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Konrad Dybcio authored
Up until now, the GPLL0_DIV MMSS input has been modeled as a fixed child of MMSS_GPLL0_DIV that's always-on. Properly representing the former in the GCC driver makes us unable to keep doing so. Consume MSS_GPLL0_DIV through fw_name ("gpll0_div") as well as add a fixed .name link to keep backwards compatibility. Reviewed-by: -
Konrad Dybcio authored
Up until now, we've been relying on some non-descript hardware magic to pinkypromise turn the clocks on for us. While new SoCs shine with that feature, MSM8998 can not always be fully trusted. Register the MMSS and GPUSS GPLL0 legs with the CCF to allow for manual enable voting. Reviewed-by:
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Konrad Dybcio authored
We've not been consuming that clock for no apparent reason. Describe it. Acked-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by:
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Bjorn Andersson authored
Merge additional MSM8998 GCC DeviceTree binding constants through a topic branch to make them available to the DeviceTree source tree as well.
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Konrad Dybcio authored
GPLL0 has two separate outputs to both GPUSS and MMSS: one that's 2-divided and one that runs at the same rate as the GPLL0 itself. Add the missing ones to the binding. Acked-by:
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- Aug 12, 2023
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Sricharan Ramabadhran authored
Add support for the global clock controller found on IPQ5018 based devices. Acked-by:
Varadarajan Narayanan <quic_varada@quicinc.com> Signed-off-by:
Gokul Sriram Palanisamy <quic_gokulsri@quicinc.com> Signed-off-by:
Sricharan Ramabadhran <quic_srichara@quicinc.com> Link: https://lore.kernel.org/r/1690533192-22220-3-git-send-email-quic_srichara@quicinc.com Signed-off-by:
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Bjorn Andersson authored
Merge the IPQ5018 GCC Devicetree binding through a topic branch, in order to the the clock defines.
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Sricharan Ramabadhran authored
This patch adds support for the global clock controller found on the IPQ5018 based devices. Reviewed-by:
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- Aug 04, 2023
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Luca Weiss authored
GPLL7 is not on by default, which causes a "gcc_sdcc2_apps_clk_src: rcg didn't update its configuration" error when booting. Set .flags = CLK_OPS_PARENT_ENABLE to fix the error. Fixes: 131abae9 ("clk: qcom: Add SM6350 GCC driver") Signed-off-by:
Luca Weiss <luca.weiss@fairphone.com> Reviewed-by:
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Konrad Dybcio authored
Use the fsleep() helper that (based on the length of the delay, see: [1]) chooses the correct sleep/delay functions. [1] https://www.kernel.org/doc/Documentation/timers/timers-howto.txt Fixes: 2cb8a39b ("clk: qcom: reset: Allow specifying custom reset delay") Signed-off-by:
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- Aug 03, 2023
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Arnd Bergmann authored
The SM_GCC_8550 symbol and others can only be built for ARM64 or when compile testing, but it gets selected by other drivers that can also be built for 32-bit ARCH_QCOM when not compile testing, which results in a Kconfig warning: WARNING: unmet direct dependencies detected for SM_GCC_8550 Depends on [n]: COMMON_CLK [=y] && COMMON_CLK_QCOM [=m] && (ARM64 || COMPILE_TEST [=n]) Selected by [m]: - SM_GPUCC_8550 [=m] && COMMON_CLK [=y] && COMMON_CLK_QCOM [=m] - SM_VIDEOCC_8550 [=m] && COMMON_CLK [=y] && COMMON_CLK_QCOM [=m] Add further 'depends on' statements to tighten this in a way that avoids the missing dependencies. Fixes: fd0b5b10 ("clk: qcom: Introduce SM8350 VIDEOCC") Fixes: 441fe711 ("clk: qcom: videocc-sm8450: Add video clock controller driver for SM8450") Fixes: f53153a3 ("clk: qcom: videocc-sm8550: Add video clock controller driver for SM8550") Signed-off-by:
Arnd Bergmann <arnd@arndb.de> Reviewed-by:
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Patrick Whewell authored
GPLL9 is not on by default, which causes a "gcc_sdcc2_apps_clk_src: rcg didn't update its configuration" error when booting. Set .flags = CLK_OPS_PARENT_ENABLE to fix the error. Fixes: 3e577092 ("clk: qcom: gcc: Add global clock controller driver for SM8250") Reviewed-by:
Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by:
Patrick Whewell <patrick.whewell@sightlineapplications.com> Reviewed-by:
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Yang Yingliang authored
The pxo_parent_data inroduced in commit bac4675a ("clk: qcom: drop lcc-mdm9615 in favour of lcc-msm8960") is only used in lcc-msm8960.c now, change it to static. Signed-off-by:
Yang Yingliang <yangyingliang@huawei.com> Reviewed-by:
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- Aug 01, 2023
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David Wronek authored
Set .flags = CLK_OPS_PARENT_ENABLE to fix "gcc_sdcc2_apps_clk_src: rcg didn't update its configuration" error. Fixes: 17269568 ("clk: qcom: Add Global Clock controller (GCC) driver for SC7180") Signed-off-by:
David Wronek <davidwronek@gmail.com> Reviewed-by:
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Yassine Oudjana authored
The CBF PLL on MSM8996 Pro has a /4 post divisor instead of /2. Handle the difference accordingly. Signed-off-by:
Yassine Oudjana <y.oudjana@protonmail.com> Reviewed-by:
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20230527093934.101335-4-y.oudjana@protonmail.com Signed-off-by:
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Yassine Oudjana authored
The CBF clock on MSM8996 Pro has a different divisor compared to MSM8996 and is therefore not fully compatible with it. Add a new compatible string to differentiate between them. Signed-off-by:
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Dmitry Baryshkov authored
The gcc and lcc devices have been switched to the DT-defined cxo_board clock. Now we can drop the manually defined cxo clock. Reviewed-by:
Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by:
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Dmitry Baryshkov authored
Convert the clock driver to specify parent data rather than parent names, to actually bind using 'clock-names' specified in the DTS rather than global clock names. Use parent_hws where possible to refer parent clocks directly, skipping the lookup. Note, the system names for xo clocks were changed from "cxo" to "cxo_board" to follow the example of other platforms. This switches the clocks to use DT-provided "cxo_board" clock instead of manually registered "cxo" clock and allows us to drop the cxo clock. Reviewed-by:
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Dmitry Baryshkov authored
The pll0_vote clock definitely should have pll0 as a parent (instead of pll8). Fixes: 7792a8d6 ("clk: mdm9615: Add support for MDM9615 Clock Controllers") Cc: stable@kernel.org Reviewed-by:
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Dmitry Baryshkov authored
The two LCC drivers, msm8960 and mdm9615 are almost the same. The only difference is the platform clock: msm8960/apq8064 use pxo, while mdm9615 uses cxo. Drop the lcc-mdm9615 in favour of using lcc-msm8960 instead. Reviewed-by:
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Dmitry Baryshkov authored
Use ARRAY_SIZE() instead of manually specifying num_parents. This makes adding/removing entries to/from parent_data easy and errorproof. Reviewed-by:
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Dmitry Baryshkov authored
The global clock controller on MDM9615 uses external CXO and PLL7 clocks. Split the qcom,gcc-mdm9615 to the separate schema file. Reviewed-by:
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Dmitry Baryshkov authored
The header file for qcom,lcc-mdm9615 and qcom,lcc-msm8960 is the same (as well as the drivers). Drop the qcom,lcc-mdm9615.h in favour of qcom,lcc-msm8960.h Reviewed-by:
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Dmitry Baryshkov authored
Describe parent clocks used by the LCC on the MDM9615 platform. It is the list as the one for msm8960/apq8064, with only difference being pxo/cxo replacement. Acked-by:
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Konrad Dybcio authored
SC8280XP, being a partial derivative of SM8350, shares almost the exact same videocc block. Extend the 8350 driver to support the bigger brother. The only notable changes are higher possible frequencies on some clocks and some switcheroo within the XO/sleep registers (probably due to some different board crystal configuration). Reviewed-by:
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Konrad Dybcio authored
SC8280XP reuses the SM8350 video clock controller block, changing just a couple tunables. Docuemnt it. Acked-by:
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- Jul 28, 2023
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Konrad Dybcio authored
The DISP_CC GDSCs have not been instructed to use the ret registers. Fix that. Fixes: 4a66e76f ("clk: qcom: Add SC8280XP display clock controller") Signed-off-by:
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- Jul 18, 2023
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Johan Hovold authored
Drivers that enable runtime PM must make sure that the controller is runtime resumed before accessing its registers to prevent the power domain from being disabled. Fixes: 892df019 ("clk: qcom: Add QCS404 TuringCC") Cc: stable@vger.kernel.org # 5.2 Cc: Bjorn Andersson <andersson@kernel.org> Signed-off-by:
Johan Hovold <johan+linaro@kernel.org> Link: https://lore.kernel.org/r/20230718132902.21430-9-johan+linaro@kernel.org Signed-off-by:
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Johan Hovold authored
Drivers that enable runtime PM must make sure that the controller is runtime resumed before accessing its registers to prevent the power domain from being disabled. Fixes: 8def929c ("clk: qcom: Add modem clock controller driver for SC7180") Cc: stable@vger.kernel.org # 5.7 Cc: Taniya Das <quic_tdas@quicinc.com> Signed-off-by:
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Johan Hovold authored
Drivers that enable runtime PM must make sure that the controller is runtime resumed before accessing its registers to prevent the power domain from being disabled. Fixes: 6cdef273 ("clk: qcom: Add Q6SSTOP clock controller for QCS404") Cc: stable@vger.kernel.org # 5.5 Signed-off-by:
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Johan Hovold authored
Drivers that enable runtime PM must make sure that the controller is runtime resumed before accessing its registers to prevent the power domain from being disabled. Fixes: 4ab43d17 ("clk: qcom: Add lpass clock controller driver for SC7280") Cc: stable@vger.kernel.org # 5.16 Cc: Taniya Das <quic_tdas@quicinc.com> Signed-off-by:
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