Commit ff344c8d authored by Vitaly Prosyak's avatar Vitaly Prosyak Committed by Alex Deucher
Browse files

drm/amd/display: Reuse dcn2 registers 



[Why & How]
Use dcn2 blender, shaper, 3dlut registers

Signed-off-by: default avatarVitaly Prosyak <vitaly.prosyak@amd.com>
Reviewed-by: default avatarCharlene Liu <Charlene.Liu@amd.com>
Acked-by: default avatarBhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Acked-by: default avatarVitaly Prosyak <Vitaly.Prosyak@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 649828f7

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h

+49 −35
Original line number Diff line number Diff line
@@ -30,16 +30,20 @@ 
#define TO_DCN20_DPP(dpp)\

	container_of(dpp, struct dcn20_dpp, base)



#define TF_REG_LIST_DCN20(id) \

	TF_REG_LIST_DCN(id), \

#define TF_REG_LIST_DCN20_COMMON_UPDATED(id) \

	SRI(CM_BLNDGAM_LUT_WRITE_EN_MASK, CM, id), \

	SRI(CM_BLNDGAM_RAMB_SLOPE_CNTL_B, CM, id), \

	SRI(CM_BLNDGAM_RAMB_SLOPE_CNTL_G, CM, id), \

	SRI(CM_BLNDGAM_RAMB_SLOPE_CNTL_R, CM, id), \

	SRI(CM_BLNDGAM_RAMA_SLOPE_CNTL_B, CM, id), \

	SRI(CM_BLNDGAM_RAMA_SLOPE_CNTL_G, CM, id), \

	SRI(CM_BLNDGAM_RAMA_SLOPE_CNTL_R, CM, id)



#define TF_REG_LIST_DCN20_COMMON(id) \

	SRI(CM_BLNDGAM_CONTROL, CM, id), \

	SRI(CM_BLNDGAM_RAMB_START_CNTL_B, CM, id), \

	SRI(CM_BLNDGAM_RAMB_START_CNTL_G, CM, id), \

	SRI(CM_BLNDGAM_RAMB_START_CNTL_R, CM, id), \

	SRI(CM_BLNDGAM_RAMB_SLOPE_CNTL_B, CM, id), \

	SRI(CM_BLNDGAM_RAMB_SLOPE_CNTL_G, CM, id), \

	SRI(CM_BLNDGAM_RAMB_SLOPE_CNTL_R, CM, id), \

	SRI(CM_BLNDGAM_RAMB_END_CNTL1_B, CM, id), \

	SRI(CM_BLNDGAM_RAMB_END_CNTL2_B, CM, id), \

	SRI(CM_BLNDGAM_RAMB_END_CNTL1_G, CM, id), \
@@ -66,9 +70,6 @@ 
	SRI(CM_BLNDGAM_RAMA_START_CNTL_B, CM, id), \

	SRI(CM_BLNDGAM_RAMA_START_CNTL_G, CM, id), \

	SRI(CM_BLNDGAM_RAMA_START_CNTL_R, CM, id), \

	SRI(CM_BLNDGAM_RAMA_SLOPE_CNTL_B, CM, id), \

	SRI(CM_BLNDGAM_RAMA_SLOPE_CNTL_G, CM, id), \

	SRI(CM_BLNDGAM_RAMA_SLOPE_CNTL_R, CM, id), \

	SRI(CM_BLNDGAM_RAMA_END_CNTL1_B, CM, id), \

	SRI(CM_BLNDGAM_RAMA_END_CNTL2_B, CM, id), \

	SRI(CM_BLNDGAM_RAMA_END_CNTL1_G, CM, id), \
@@ -147,7 +148,12 @@ 
	SRI(CM_SHAPER_RAMA_REGION_28_29, CM, id), \

	SRI(CM_SHAPER_RAMA_REGION_30_31, CM, id), \

	SRI(CM_SHAPER_RAMA_REGION_32_33, CM, id), \

	SRI(CM_SHAPER_LUT_INDEX, CM, id), \

	SRI(CM_SHAPER_LUT_INDEX, CM, id)



#define TF_REG_LIST_DCN20(id) \

	TF_REG_LIST_DCN(id), \

	TF_REG_LIST_DCN20_COMMON(id), \

	TF_REG_LIST_DCN20_COMMON_UPDATED(id), \

	SRI(CURSOR_CONTROL, CURSOR0_, id), \

	SRI(ALPHA_2BIT_LUT, CNVC_CFG, id), \

	SRI(FCNV_FP_BIAS_R, CNVC_CFG, id), \
@@ -166,27 +172,41 @@ 
	SRI(OBUF_MEM_PWR_CTRL, DSCL, id),\

	SRI(DSCL_MEM_PWR_CTRL, DSCL, id)



#define TF_REG_LIST_SH_MASK_DCN20(mask_sh)\

	TF_REG_LIST_SH_MASK_DCN(mask_sh), \



#define TF_REG_LIST_SH_MASK_DCN20_UPDATED(mask_sh)\

	TF_SF(CM0_CM_BLNDGAM_RAMB_SLOPE_CNTL_B, CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B, mask_sh), \

	TF_SF(CM0_CM_BLNDGAM_RAMB_SLOPE_CNTL_G, CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G, mask_sh), \

	TF_SF(CM0_CM_BLNDGAM_RAMB_SLOPE_CNTL_R, CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R, mask_sh), \

	TF_SF(CM0_CM_BLNDGAM_RAMB_END_CNTL1_B, CM_BLNDGAM_RAMB_EXP_REGION_END_B, mask_sh), \

	TF_SF(CM0_CM_BLNDGAM_RAMB_END_CNTL1_G, CM_BLNDGAM_RAMB_EXP_REGION_END_G, mask_sh), \

	TF_SF(CM0_CM_BLNDGAM_RAMB_END_CNTL1_R, CM_BLNDGAM_RAMB_EXP_REGION_END_R, mask_sh), \

	TF_SF(CM0_CM_BLNDGAM_RAMA_SLOPE_CNTL_B, CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B, mask_sh), \

	TF_SF(CM0_CM_BLNDGAM_RAMA_SLOPE_CNTL_G, CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G, mask_sh), \

	TF_SF(CM0_CM_BLNDGAM_RAMA_SLOPE_CNTL_R, CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R, mask_sh), \

	TF_SF(CM0_CM_BLNDGAM_RAMA_END_CNTL1_B, CM_BLNDGAM_RAMA_EXP_REGION_END_B, mask_sh), \

	TF_SF(CM0_CM_BLNDGAM_RAMA_END_CNTL1_G, CM_BLNDGAM_RAMA_EXP_REGION_END_G, mask_sh), \

	TF_SF(CM0_CM_BLNDGAM_RAMA_END_CNTL1_R, CM_BLNDGAM_RAMA_EXP_REGION_END_R, mask_sh), \

	TF_SF(CM0_CM_BLNDGAM_RAMA_END_CNTL2_B, CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B, mask_sh), \

	TF_SF(CM0_CM_BLNDGAM_RAMA_END_CNTL2_G, CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_G, mask_sh), \

	TF_SF(CM0_CM_BLNDGAM_RAMA_END_CNTL2_R, CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_R, mask_sh), \

	TF_SF(CM0_CM_BLNDGAM_CONTROL, CM_BLNDGAM_LUT_MODE, mask_sh), \

	TF_SF(CM0_CM_BLNDGAM_LUT_WRITE_EN_MASK, CM_BLNDGAM_LUT_WRITE_EN_MASK, mask_sh), \

	TF_SF(CM0_CM_BLNDGAM_LUT_WRITE_EN_MASK, CM_BLNDGAM_LUT_WRITE_SEL, mask_sh), \

	TF_SF(CM0_CM_BLNDGAM_LUT_WRITE_EN_MASK, CM_BLNDGAM_CONFIG_STATUS, mask_sh), \

	TF_SF(CM0_CM_SHAPER_CONTROL, CM_SHAPER_LUT_MODE, mask_sh)





#define TF_REG_LIST_SH_MASK_DCN20_COMMON(mask_sh)\

	TF_SF(CM0_CM_3DLUT_MODE, CM_3DLUT_MODE, mask_sh), \

	TF_SF(CM0_CM_BLNDGAM_RAMB_START_CNTL_B, CM_BLNDGAM_RAMB_EXP_REGION_START_B, mask_sh), \

	TF_SF(CM0_CM_BLNDGAM_RAMB_START_CNTL_B, CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_B, mask_sh), \

	TF_SF(CM0_CM_BLNDGAM_RAMB_START_CNTL_G, CM_BLNDGAM_RAMB_EXP_REGION_START_G, mask_sh), \

	TF_SF(CM0_CM_BLNDGAM_RAMB_START_CNTL_G, CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_G, mask_sh), \

	TF_SF(CM0_CM_BLNDGAM_RAMB_START_CNTL_R, CM_BLNDGAM_RAMB_EXP_REGION_START_R, mask_sh), \

	TF_SF(CM0_CM_BLNDGAM_RAMB_START_CNTL_R, CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_R, mask_sh), \

	TF_SF(CM0_CM_BLNDGAM_RAMB_SLOPE_CNTL_B, CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B, mask_sh), \

	TF_SF(CM0_CM_BLNDGAM_RAMB_SLOPE_CNTL_G, CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G, mask_sh), \

	TF_SF(CM0_CM_BLNDGAM_RAMB_SLOPE_CNTL_R, CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R, mask_sh), \

	TF_SF(CM0_CM_BLNDGAM_RAMB_END_CNTL1_B, CM_BLNDGAM_RAMB_EXP_REGION_END_B, mask_sh), \

	TF_SF(CM0_CM_BLNDGAM_RAMB_END_CNTL2_B, CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_B, mask_sh), \

	TF_SF(CM0_CM_BLNDGAM_RAMB_END_CNTL2_B, CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_B, mask_sh), \

	TF_SF(CM0_CM_BLNDGAM_RAMB_END_CNTL1_G, CM_BLNDGAM_RAMB_EXP_REGION_END_G, mask_sh), \

	TF_SF(CM0_CM_BLNDGAM_RAMB_END_CNTL2_G, CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_G, mask_sh), \

	TF_SF(CM0_CM_BLNDGAM_RAMB_END_CNTL2_G, CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_G, mask_sh), \

	TF_SF(CM0_CM_BLNDGAM_RAMB_END_CNTL1_R, CM_BLNDGAM_RAMB_EXP_REGION_END_R, mask_sh), \

	TF_SF(CM0_CM_BLNDGAM_RAMB_END_CNTL2_R, CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_R, mask_sh), \

	TF_SF(CM0_CM_BLNDGAM_RAMB_END_CNTL2_R, CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_R, mask_sh), \

	TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_0_1, CM_BLNDGAM_RAMB_EXP_REGION0_LUT_OFFSET, mask_sh), \

	TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_0_1, CM_BLNDGAM_RAMB_EXP_REGION0_NUM_SEGMENTS, mask_sh), \

	TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_0_1, CM_BLNDGAM_RAMB_EXP_REGION1_LUT_OFFSET, mask_sh), \
@@ -261,18 +281,9 @@ 
	TF_SF(CM0_CM_BLNDGAM_RAMA_START_CNTL_G, CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_G, mask_sh), \

	TF_SF(CM0_CM_BLNDGAM_RAMA_START_CNTL_R, CM_BLNDGAM_RAMA_EXP_REGION_START_R, mask_sh), \

	TF_SF(CM0_CM_BLNDGAM_RAMA_START_CNTL_R, CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_R, mask_sh), \

	TF_SF(CM0_CM_BLNDGAM_RAMA_SLOPE_CNTL_B, CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B, mask_sh), \

	TF_SF(CM0_CM_BLNDGAM_RAMA_SLOPE_CNTL_G, CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G, mask_sh), \

	TF_SF(CM0_CM_BLNDGAM_RAMA_SLOPE_CNTL_R, CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R, mask_sh), \

	TF_SF(CM0_CM_BLNDGAM_RAMA_END_CNTL1_B, CM_BLNDGAM_RAMA_EXP_REGION_END_B, mask_sh), \

	TF_SF(CM0_CM_BLNDGAM_RAMA_END_CNTL2_B, CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B, mask_sh), \

	TF_SF(CM0_CM_BLNDGAM_RAMA_END_CNTL2_B, CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B, mask_sh), \

	TF_SF(CM0_CM_BLNDGAM_RAMA_END_CNTL1_G, CM_BLNDGAM_RAMA_EXP_REGION_END_G, mask_sh), \

	TF_SF(CM0_CM_BLNDGAM_RAMA_END_CNTL2_G, CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_G, mask_sh), \

	TF_SF(CM0_CM_BLNDGAM_RAMA_END_CNTL2_G, CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_G, mask_sh), \

	TF_SF(CM0_CM_BLNDGAM_RAMA_END_CNTL1_R, CM_BLNDGAM_RAMA_EXP_REGION_END_R, mask_sh), \

	TF_SF(CM0_CM_BLNDGAM_RAMA_END_CNTL2_R, CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_R, mask_sh), \

	TF_SF(CM0_CM_BLNDGAM_RAMA_END_CNTL2_R, CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_R, mask_sh), \

	TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_0_1, CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET, mask_sh), \

	TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_0_1, CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS, mask_sh), \

	TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_0_1, CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET, mask_sh), \
@@ -341,9 +352,6 @@ 
	TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_32_33, CM_BLNDGAM_RAMA_EXP_REGION32_NUM_SEGMENTS, mask_sh), \

	TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_32_33, CM_BLNDGAM_RAMA_EXP_REGION33_LUT_OFFSET, mask_sh), \

	TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_32_33, CM_BLNDGAM_RAMA_EXP_REGION33_NUM_SEGMENTS, mask_sh), \

	TF_SF(CM0_CM_BLNDGAM_LUT_WRITE_EN_MASK, CM_BLNDGAM_LUT_WRITE_EN_MASK, mask_sh), \

	TF_SF(CM0_CM_BLNDGAM_LUT_WRITE_EN_MASK, CM_BLNDGAM_LUT_WRITE_SEL, mask_sh), \

	TF_SF(CM0_CM_BLNDGAM_LUT_WRITE_EN_MASK, CM_BLNDGAM_CONFIG_STATUS, mask_sh), \

	TF_SF(CM0_CM_BLNDGAM_LUT_INDEX, CM_BLNDGAM_LUT_INDEX, mask_sh), \

	TF_SF(CM0_CM_BLNDGAM_LUT_DATA, CM_BLNDGAM_LUT_DATA, mask_sh), \

	TF_SF(CM0_CM_MEM_PWR_CTRL, BLNDGAM_MEM_PWR_FORCE, mask_sh), \
@@ -356,7 +364,6 @@ 
	TF_SF(CM0_CM_3DLUT_READ_WRITE_CONTROL, CM_3DLUT_WRITE_EN_MASK, mask_sh), \

	TF_SF(CM0_CM_3DLUT_READ_WRITE_CONTROL, CM_3DLUT_RAM_SEL, mask_sh), \

	TF_SF(CM0_CM_3DLUT_READ_WRITE_CONTROL, CM_3DLUT_30BIT_EN, mask_sh), \

	TF_SF(CM0_CM_3DLUT_READ_WRITE_CONTROL, CM_3DLUT_CONFIG_STATUS, mask_sh), \

	TF_SF(CM0_CM_3DLUT_READ_WRITE_CONTROL, CM_3DLUT_READ_SEL, mask_sh), \

	TF_SF(CM0_CM_SHAPER_CONTROL, CM_SHAPER_LUT_MODE, mask_sh), \

	TF_SF(CM0_CM_SHAPER_RAMB_START_CNTL_B, CM_SHAPER_RAMB_EXP_REGION_START_B, mask_sh), \
@@ -521,9 +528,14 @@ 
	TF_SF(CM0_CM_SHAPER_RAMA_REGION_32_33, CM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS, mask_sh), \

	TF_SF(CM0_CM_SHAPER_LUT_WRITE_EN_MASK, CM_SHAPER_LUT_WRITE_EN_MASK, mask_sh), \

	TF_SF(CM0_CM_SHAPER_LUT_WRITE_EN_MASK, CM_SHAPER_LUT_WRITE_SEL, mask_sh), \

	TF_SF(CM0_CM_SHAPER_LUT_WRITE_EN_MASK, CM_SHAPER_CONFIG_STATUS, mask_sh), \

	TF_SF(CM0_CM_SHAPER_LUT_INDEX, CM_SHAPER_LUT_INDEX, mask_sh), \

	TF_SF(CM0_CM_SHAPER_LUT_DATA, CM_SHAPER_LUT_DATA, mask_sh), \

	TF_SF(CM0_CM_SHAPER_LUT_DATA, CM_SHAPER_LUT_DATA, mask_sh)





#define TF_REG_LIST_SH_MASK_DCN20(mask_sh)\

	TF_REG_LIST_SH_MASK_DCN(mask_sh), \

	TF_REG_LIST_SH_MASK_DCN20_COMMON(mask_sh), \

	TF_REG_LIST_SH_MASK_DCN20_UPDATED(mask_sh), \

	TF_SF(CM0_CM_DGAM_LUT_WRITE_EN_MASK, CM_DGAM_CONFIG_STATUS, mask_sh), \

	TF_SF(CM0_CM_CONTROL, CM_BYPASS, mask_sh), \

	TF_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_MODE, mask_sh), \
@@ -560,6 +572,7 @@ 
	TF_SF(DSCL0_OBUF_MEM_PWR_CTRL, OBUF_MEM_PWR_FORCE, mask_sh),\

	TF_SF(DSCL0_DSCL_MEM_PWR_CTRL, LUT_MEM_PWR_FORCE, mask_sh)





#define TF_REG_FIELD_LIST_DCN2_0(type) \

	TF_REG_FIELD_LIST(type) \

	type CM_BLNDGAM_LUT_DATA; \
@@ -593,6 +606,7 @@ 
	type OBUF_MEM_PWR_FORCE;\

	type LUT_MEM_PWR_FORCE





struct dcn2_dpp_shift {

	TF_REG_FIELD_LIST_DCN2_0(uint8_t);

};

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c

+5 −5
Original line number Diff line number Diff line
@@ -508,7 +508,7 @@ static void dcn20_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx) 
}





static void dcn20_disable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx)

void dcn20_disable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx)

{

	DC_LOGGER_INIT(dc->ctx->logger);
@@ -688,7 +688,7 @@ bool dcn20_set_output_transfer_func(struct pipe_ctx *pipe_ctx, 
	return true;

}



static bool dcn20_set_blend_lut(

bool dcn20_set_blend_lut(

	struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state)

{

	struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
@@ -710,7 +710,7 @@ static bool dcn20_set_blend_lut( 
	return result;

}



static bool dcn20_set_shaper_3dlut(

bool dcn20_set_shaper_3dlut(

	struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state)

{

	struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
@@ -923,7 +923,7 @@ static void dcn20_power_on_plane( 
	}

}



static void dcn20_enable_plane(

void dcn20_enable_plane(

	struct dc *dc,

	struct pipe_ctx *pipe_ctx,

	struct dc_state *context)
@@ -1021,7 +1021,7 @@ void dcn20_pipe_control_lock_global( 
	}

}



static void dcn20_pipe_control_lock(

void dcn20_pipe_control_lock(

	struct dc *dc,

	struct pipe_ctx *pipe,

	bool lock)

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h

+14 −0
Original line number Diff line number Diff line
@@ -96,4 +96,18 @@ void dcn20_init_blank( 
	   struct dc *dc,

	   struct timing_generator *tg);

void dcn20_display_init(struct dc *dc);

void dcn20_pipe_control_lock(

	struct dc *dc,

	struct pipe_ctx *pipe,

	bool lock);

void dcn20_disable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx);

void dcn20_enable_plane(

	struct dc *dc,

	struct pipe_ctx *pipe_ctx,

	struct dc_state *context);

bool dcn20_set_blend_lut(

	struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state);

bool dcn20_set_shaper_3dlut(

	struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state);



#endif /* __DC_HWSS_DCN20_H__ */