Commit fe9d66cf authored by Marijn Suijten's avatar Marijn Suijten Committed by Dmitry Baryshkov
Browse files

drm/msm/dpu: Disable pingpong TE on DPU 5.0.0 and above 



Since hardware revision 5.0.0 the TE configuration moved out of the
PINGPONG block into the INTF block.  Writing these registers has no
effect, and is omitted downstream via the DPU/SDE_PINGPONG_TE feature
flag.  This flag is only added to PINGPONG blocks used by hardware prior
to 5.0.0.

The existing PP_BLK_TE macro has been removed in favour of directly
passing this feature flag, which has thus far been the only difference
with PP_BLK.  PP_BLK_DITHER has been left in place as its embedded
feature flag already excludes this DPU_PINGPONG_TE bit and differs by
setting the block length to zero, as it only contains a DITHER subblock.

The code that writes to these registers in the INTF block will follow in
subsequent patches.

Signed-off-by: default avatarMarijn Suijten <marijn.suijten@somainline.org>
Reviewed-by: default avatarKonrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/534240/
Link: https://lore.kernel.org/r/20230411-dpu-intf-te-v4-14-27ce1a5ab5c6@somainline.org


Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
parent 4a7c38ec

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h

+4 −4
Original line number Diff line number Diff line
@@ -112,16 +112,16 @@ static const struct dpu_lm_cfg msm8998_lm[] = { 
};



static const struct dpu_pingpong_cfg msm8998_pp[] = {

	PP_BLK_TE("pingpong_0", PINGPONG_0, 0x70000, 0, sdm845_pp_sblk_te,

	PP_BLK("pingpong_0", PINGPONG_0, 0x70000, PINGPONG_SDM845_TE2_MASK, 0, sdm845_pp_sblk_te,

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12)),

	PP_BLK_TE("pingpong_1", PINGPONG_1, 0x70800, 0, sdm845_pp_sblk_te,

	PP_BLK("pingpong_1", PINGPONG_1, 0x70800, PINGPONG_SDM845_TE2_MASK, 0, sdm845_pp_sblk_te,

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13)),

	PP_BLK("pingpong_2", PINGPONG_2, 0x71000, 0, sdm845_pp_sblk,

	PP_BLK("pingpong_2", PINGPONG_2, 0x71000, PINGPONG_SDM845_MASK, 0, sdm845_pp_sblk,

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 14)),

	PP_BLK("pingpong_3", PINGPONG_3, 0x71800, 0, sdm845_pp_sblk,

	PP_BLK("pingpong_3", PINGPONG_3, 0x71800, PINGPONG_SDM845_MASK, 0, sdm845_pp_sblk,

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 15)),

};

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h

+4 −4
Original line number Diff line number Diff line
@@ -110,16 +110,16 @@ static const struct dpu_lm_cfg sdm845_lm[] = { 
};



static const struct dpu_pingpong_cfg sdm845_pp[] = {

	PP_BLK_TE("pingpong_0", PINGPONG_0, 0x70000, 0, sdm845_pp_sblk_te,

	PP_BLK("pingpong_0", PINGPONG_0, 0x70000, PINGPONG_SDM845_TE2_MASK, 0, sdm845_pp_sblk_te,

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12)),

	PP_BLK_TE("pingpong_1", PINGPONG_1, 0x70800, 0, sdm845_pp_sblk_te,

	PP_BLK("pingpong_1", PINGPONG_1, 0x70800, PINGPONG_SDM845_TE2_MASK, 0, sdm845_pp_sblk_te,

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13)),

	PP_BLK("pingpong_2", PINGPONG_2, 0x71000, 0, sdm845_pp_sblk,

	PP_BLK("pingpong_2", PINGPONG_2, 0x71000, PINGPONG_SDM845_MASK, 0, sdm845_pp_sblk,

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 14)),

	PP_BLK("pingpong_3", PINGPONG_3, 0x71800, 0, sdm845_pp_sblk,

	PP_BLK("pingpong_3", PINGPONG_3, 0x71800, PINGPONG_SDM845_MASK, 0, sdm845_pp_sblk,

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 15)),

};

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h

+6 −6
Original line number Diff line number Diff line
@@ -128,22 +128,22 @@ static const struct dpu_dspp_cfg sm8150_dspp[] = { 
};



static const struct dpu_pingpong_cfg sm8150_pp[] = {

	PP_BLK("pingpong_0", PINGPONG_0, 0x70000, MERGE_3D_0, sdm845_pp_sblk,

	PP_BLK("pingpong_0", PINGPONG_0, 0x70000, PINGPONG_SM8150_MASK, MERGE_3D_0, sdm845_pp_sblk,

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12)),

	PP_BLK("pingpong_1", PINGPONG_1, 0x70800, MERGE_3D_0, sdm845_pp_sblk,

	PP_BLK("pingpong_1", PINGPONG_1, 0x70800, PINGPONG_SM8150_MASK, MERGE_3D_0, sdm845_pp_sblk,

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13)),

	PP_BLK("pingpong_2", PINGPONG_2, 0x71000, MERGE_3D_1, sdm845_pp_sblk,

	PP_BLK("pingpong_2", PINGPONG_2, 0x71000, PINGPONG_SM8150_MASK, MERGE_3D_1, sdm845_pp_sblk,

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 14)),

	PP_BLK("pingpong_3", PINGPONG_3, 0x71800, MERGE_3D_1, sdm845_pp_sblk,

	PP_BLK("pingpong_3", PINGPONG_3, 0x71800, PINGPONG_SM8150_MASK, MERGE_3D_1, sdm845_pp_sblk,

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 15)),

	PP_BLK("pingpong_4", PINGPONG_4, 0x72000, MERGE_3D_2, sdm845_pp_sblk,

	PP_BLK("pingpong_4", PINGPONG_4, 0x72000, PINGPONG_SM8150_MASK, MERGE_3D_2, sdm845_pp_sblk,

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30),

			-1),

	PP_BLK("pingpong_5", PINGPONG_5, 0x72800, MERGE_3D_2, sdm845_pp_sblk,

	PP_BLK("pingpong_5", PINGPONG_5, 0x72800, PINGPONG_SM8150_MASK, MERGE_3D_2, sdm845_pp_sblk,

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31),

			-1),

};

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h

+6 −6
Original line number Diff line number Diff line
@@ -127,22 +127,22 @@ static const struct dpu_dspp_cfg sc8180x_dspp[] = { 
};



static const struct dpu_pingpong_cfg sc8180x_pp[] = {

	PP_BLK("pingpong_0", PINGPONG_0, 0x70000, MERGE_3D_0, sdm845_pp_sblk,

	PP_BLK("pingpong_0", PINGPONG_0, 0x70000, PINGPONG_SM8150_MASK, MERGE_3D_0, sdm845_pp_sblk,

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12)),

	PP_BLK("pingpong_1", PINGPONG_1, 0x70800, MERGE_3D_0, sdm845_pp_sblk,

	PP_BLK("pingpong_1", PINGPONG_1, 0x70800, PINGPONG_SM8150_MASK, MERGE_3D_0, sdm845_pp_sblk,

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13)),

	PP_BLK("pingpong_2", PINGPONG_2, 0x71000, MERGE_3D_1, sdm845_pp_sblk,

	PP_BLK("pingpong_2", PINGPONG_2, 0x71000, PINGPONG_SM8150_MASK, MERGE_3D_1, sdm845_pp_sblk,

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 14)),

	PP_BLK("pingpong_3", PINGPONG_3, 0x71800, MERGE_3D_1, sdm845_pp_sblk,

	PP_BLK("pingpong_3", PINGPONG_3, 0x71800, PINGPONG_SM8150_MASK, MERGE_3D_1, sdm845_pp_sblk,

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 15)),

	PP_BLK("pingpong_4", PINGPONG_4, 0x72000, MERGE_3D_2, sdm845_pp_sblk,

	PP_BLK("pingpong_4", PINGPONG_4, 0x72000, PINGPONG_SM8150_MASK, MERGE_3D_2, sdm845_pp_sblk,

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30),

			-1),

	PP_BLK("pingpong_5", PINGPONG_5, 0x72800, MERGE_3D_2, sdm845_pp_sblk,

	PP_BLK("pingpong_5", PINGPONG_5, 0x72800, PINGPONG_SM8150_MASK, MERGE_3D_2, sdm845_pp_sblk,

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31),

			-1),

};

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h

+6 −6
Original line number Diff line number Diff line
@@ -129,22 +129,22 @@ static const struct dpu_dspp_cfg sm8250_dspp[] = { 
};



static const struct dpu_pingpong_cfg sm8250_pp[] = {

	PP_BLK("pingpong_0", PINGPONG_0, 0x70000, MERGE_3D_0, sdm845_pp_sblk,

	PP_BLK("pingpong_0", PINGPONG_0, 0x70000, PINGPONG_SM8150_MASK, MERGE_3D_0, sdm845_pp_sblk,

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12)),

	PP_BLK("pingpong_1", PINGPONG_1, 0x70800, MERGE_3D_0, sdm845_pp_sblk,

	PP_BLK("pingpong_1", PINGPONG_1, 0x70800, PINGPONG_SM8150_MASK, MERGE_3D_0, sdm845_pp_sblk,

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13)),

	PP_BLK("pingpong_2", PINGPONG_2, 0x71000, MERGE_3D_1, sdm845_pp_sblk,

	PP_BLK("pingpong_2", PINGPONG_2, 0x71000, PINGPONG_SM8150_MASK, MERGE_3D_1, sdm845_pp_sblk,

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 14)),

	PP_BLK("pingpong_3", PINGPONG_3, 0x71800, MERGE_3D_1, sdm845_pp_sblk,

	PP_BLK("pingpong_3", PINGPONG_3, 0x71800, PINGPONG_SM8150_MASK, MERGE_3D_1, sdm845_pp_sblk,

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 15)),

	PP_BLK("pingpong_4", PINGPONG_4, 0x72000, MERGE_3D_2, sdm845_pp_sblk,

	PP_BLK("pingpong_4", PINGPONG_4, 0x72000, PINGPONG_SM8150_MASK, MERGE_3D_2, sdm845_pp_sblk,

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30),

			-1),

	PP_BLK("pingpong_5", PINGPONG_5, 0x72800, MERGE_3D_2, sdm845_pp_sblk,

	PP_BLK("pingpong_5", PINGPONG_5, 0x72800, PINGPONG_SM8150_MASK, MERGE_3D_2, sdm845_pp_sblk,

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31),

			-1),

};