Commit fc48cf43 authored by Olof Johansson's avatar Olof Johansson
Browse files

Merge tag 'renesas-arm-dt-for-v4.20' of... 

Merge tag 'renesas-arm-dt-for-v4.20' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt

Renesas ARM Based SoC DT Updates for v4.20

* R-Car Gen1 SoCs: Include product name in DTSI files for ease of maintenance
* R-Car Gen2 SoCs:
  - Convert to new DU DT bindings
  - Correct SATA device sizes to 2 MiB
* R-Car H2 (r8a7790) based Porter board: Add DA9063 OnKey PMIC node
* R-Car E2 (r8a7794) based Silk board: Add DA9063 PMIC, RTC and OnKey nodes
* R-Car M2-N (r8a7793) based Gose board: Add DA9210 node for CPU DVFS
* RZ/G1C (R8A77470) SoC:
  - Add GPIO nodes
  - Add PFC support
  - Use r8a77470-sysc binding definitions
* RZ/G1C (r8a77470) iW-RainboW-G23S dev platform:
  - Specify EtherAVB PHY IRQ
  - Add pinctl support for scif1
* RZ/N1D (r9a06g032) SoC: Use r9a06g032-sysctrl binding definitions

* tag 'renesas-arm-dt-for-v4.20' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas

:
  ARM: dts: r9a06g032: Use r9a06g032-sysctrl binding definitions
  ARM: dts: Include R-Car Gen1 product name in DTSI files
  ARM: dts: stout: Add DA9063 OnKey node
  ARM: dts: silk: Add DA9063 RTC and OnKey node
  ARM: dts: iwg23s-sbc: specify EtherAVB PHY IRQ
  ARM: dts: r8a77470: Add GPIO support
  ARM: dts: silk: Add DA9063 PMIC node
  ARM: dts: gose: Add DA9210 node for CPU DVFS
  ARM: dts: rcar-gen2: Convert to new DU DT bindings
  ARM: dts: iwg23s-sbc: Add pinctl support for scif1
  ARM: dts: r8a77470: Add PFC support
  ARM: dts: r8a77470: Use r8a77470-sysc binding definitions
  ARM: dts: rcar: Correct SATA device sizes to 2 MiB

Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents 7adb6bab 1926bd6b

arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts

+12 −0
Original line number Diff line number Diff line
@@ -35,6 +35,8 @@ &avb { 


	phy3: ethernet-phy@3 {

		reg = <3>;

		interrupt-parent = <&gpio5>;

		interrupts = <16 IRQ_TYPE_LEVEL_LOW>;

		micrel,led-mode = <1>;

	};

};
@@ -43,6 +45,16 @@ &extal_clk { 
	clock-frequency = <20000000>;

};



&pfc {

	scif1_pins: scif1 {

		groups = "scif1_data_b";

		function = "scif1";

	};

};



&scif1 {

	pinctrl-0 = <&scif1_pins>;

	pinctrl-names = "default";



	status = "okay";

};

arch/arm/boot/dts/r8a77470.dtsi

+110 −13
Original line number Diff line number Diff line
@@ -8,6 +8,7 @@ 
#include <dt-bindings/interrupt-controller/irq.h>

#include <dt-bindings/interrupt-controller/arm-gic.h>

#include <dt-bindings/clock/r8a77470-cpg-mssr.h>

#include <dt-bindings/power/r8a77470-sysc.h>

/ {

	compatible = "renesas,r8a77470";

	#address-cells = <2>;
@@ -23,7 +24,7 @@ cpu0: cpu@0 { 
			reg = <0>;

			clock-frequency = <1000000000>;

			clocks = <&cpg CPG_CORE R8A77470_CLK_Z2>;

			power-domains = <&sysc 5>;

			power-domains = <&sysc R8A77470_PD_CA7_CPU0>;

			next-level-cache = <&L2_CA7>;

		};
@@ -32,7 +33,7 @@ L2_CA7: cache-controller-0 { 
			compatible = "cache";

			cache-unified;

			cache-level = <2>;

			power-domains = <&sysc 21>;

			power-domains = <&sysc R8A77470_PD_CA7_SCU>;

		};

	};
@@ -60,6 +61,102 @@ soc { 
		#size-cells = <2>;

		ranges;



		gpio0: gpio@e6050000 {

			compatible = "renesas,gpio-r8a77470",

				     "renesas,rcar-gen2-gpio";

			reg = <0 0xe6050000 0 0x50>;

			interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;

			#gpio-cells = <2>;

			gpio-controller;

			gpio-ranges = <&pfc 0 0 23>;

			#interrupt-cells = <2>;

			interrupt-controller;

			clocks = <&cpg CPG_MOD 912>;

			power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;

			resets = <&cpg 912>;

		};



		gpio1: gpio@e6051000 {

			compatible = "renesas,gpio-r8a77470",

				     "renesas,rcar-gen2-gpio";

			reg = <0 0xe6051000 0 0x50>;

			interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;

			#gpio-cells = <2>;

			gpio-controller;

			gpio-ranges = <&pfc 0 32 23>;

			#interrupt-cells = <2>;

			interrupt-controller;

			clocks = <&cpg CPG_MOD 911>;

			power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;

			resets = <&cpg 911>;

		};



		gpio2: gpio@e6052000 {

			compatible = "renesas,gpio-r8a77470",

				     "renesas,rcar-gen2-gpio";

			reg = <0 0xe6052000 0 0x50>;

			interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;

			#gpio-cells = <2>;

			gpio-controller;

			gpio-ranges = <&pfc 0 64 32>;

			#interrupt-cells = <2>;

			interrupt-controller;

			clocks = <&cpg CPG_MOD 910>;

			power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;

			resets = <&cpg 910>;

		};



		gpio3: gpio@e6053000 {

			compatible = "renesas,gpio-r8a77470",

				     "renesas,rcar-gen2-gpio";

			reg = <0 0xe6053000 0 0x50>;

			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;

			#gpio-cells = <2>;

			gpio-controller;

			gpio-ranges = <&pfc 0 96 30>;

			gpio-reserved-ranges = <17 10>;

			#interrupt-cells = <2>;

			interrupt-controller;

			clocks = <&cpg CPG_MOD 909>;

			power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;

			resets = <&cpg 909>;

		};



		gpio4: gpio@e6054000 {

			compatible = "renesas,gpio-r8a77470",

				     "renesas,rcar-gen2-gpio";

			reg = <0 0xe6054000 0 0x50>;

			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;

			#gpio-cells = <2>;

			gpio-controller;

			gpio-ranges = <&pfc 0 128 26>;

			#interrupt-cells = <2>;

			interrupt-controller;

			clocks = <&cpg CPG_MOD 908>;

			power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;

			resets = <&cpg 908>;

		};



		gpio5: gpio@e6055000 {

			compatible = "renesas,gpio-r8a77470",

				     "renesas,rcar-gen2-gpio";

			reg = <0 0xe6055000 0 0x50>;

			interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;

			#gpio-cells = <2>;

			gpio-controller;

			gpio-ranges = <&pfc 0 160 32>;

			#interrupt-cells = <2>;

			interrupt-controller;

			clocks = <&cpg CPG_MOD 907>;

			power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;

			resets = <&cpg 907>;

		};



		pfc: pin-controller@e6060000 {

			compatible = "renesas,pfc-r8a77470";

			reg = <0 0xe6060000 0 0x118>;

		};



		cpg: clock-controller@e6150000 {

			compatible = "renesas,r8a77470-cpg-mssr";

			reg = <0 0xe6150000 0 0x1000>;
@@ -97,7 +194,7 @@ irqc: interrupt-controller@e61c0000 { 
				     <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 407>;

			power-domains = <&sysc 32>;

			power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;

			resets = <&cpg 407>;

		};
@@ -151,7 +248,7 @@ GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH 
					  "ch12", "ch13", "ch14";

			clocks = <&cpg CPG_MOD 219>;

			clock-names = "fck";

			power-domains = <&sysc 32>;

			power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;

			resets = <&cpg 219>;

			#dma-cells = <1>;

			dma-channels = <15>;
@@ -184,7 +281,7 @@ GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH 
					  "ch12", "ch13", "ch14";

			clocks = <&cpg CPG_MOD 218>;

			clock-names = "fck";

			power-domains = <&sysc 32>;

			power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;

			resets = <&cpg 218>;

			#dma-cells = <1>;

			dma-channels = <15>;
@@ -196,7 +293,7 @@ avb: ethernet@e6800000 { 
			reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;

			interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 812>;

			power-domains = <&sysc 32>;

			power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;

			resets = <&cpg 812>;

			#address-cells = <1>;

			#size-cells = <0>;
@@ -214,7 +311,7 @@ scif0: serial@e6e60000 { 
			dmas = <&dmac0 0x29>, <&dmac0 0x2a>,

			       <&dmac1 0x29>, <&dmac1 0x2a>;

			dma-names = "tx", "rx", "tx", "rx";

			power-domains = <&sysc 32>;

			power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;

			resets = <&cpg 721>;

			status = "disabled";

		};
@@ -230,7 +327,7 @@ scif1: serial@e6e68000 { 
			dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,

			       <&dmac1 0x2d>, <&dmac1 0x2e>;

			dma-names = "tx", "rx", "tx", "rx";

			power-domains = <&sysc 32>;

			power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;

			resets = <&cpg 720>;

			status = "disabled";

		};
@@ -246,7 +343,7 @@ scif2: serial@e6e58000 { 
			dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,

			       <&dmac1 0x2b>, <&dmac1 0x2c>;

			dma-names = "tx", "rx", "tx", "rx";

			power-domains = <&sysc 32>;

			power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;

			resets = <&cpg 719>;

			status = "disabled";

		};
@@ -262,7 +359,7 @@ scif3: serial@e6ea8000 { 
			dmas = <&dmac0 0x2f>, <&dmac0 0x30>,

			       <&dmac1 0x2f>, <&dmac1 0x30>;

			dma-names = "tx", "rx", "tx", "rx";

			power-domains = <&sysc 32>;

			power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;

			resets = <&cpg 718>;

			status = "disabled";

		};
@@ -278,7 +375,7 @@ scif4: serial@e6ee0000 { 
			dmas = <&dmac0 0xfb>, <&dmac0 0xfc>,

			       <&dmac1 0xfb>, <&dmac1 0xfc>;

			dma-names = "tx", "rx", "tx", "rx";

			power-domains = <&sysc 32>;

			power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;

			resets = <&cpg 715>;

			status = "disabled";

		};
@@ -294,7 +391,7 @@ scif5: serial@e6ee8000 { 
			dmas = <&dmac0 0xfd>, <&dmac0 0xfe>,

			       <&dmac1 0xfd>, <&dmac1 0xfe>;

			dma-names = "tx", "rx", "tx", "rx";

			power-domains = <&sysc 32>;

			power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;

			resets = <&cpg 714>;

			status = "disabled";

		};
@@ -309,7 +406,7 @@ gic: interrupt-controller@f1001000 { 
			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;

			clocks = <&cpg CPG_MOD 408>;

			clock-names = "clk";

			power-domains = <&sysc 32>;

			power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;

			resets = <&cpg 408>;

		};

arch/arm/boot/dts/r8a7778.dtsi

+1 −1
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0

/*

 * Device Tree Source for Renesas r8a7778

 * Device Tree Source for the R-Car M1A (R8A77781) SoC

 *

 * Copyright (C) 2013  Renesas Solutions Corp.

 * Copyright (C) 2013  Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>

arch/arm/boot/dts/r8a7779.dtsi

+2 −2
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0

/*

 * Device Tree Source for Renesas r8a7779

 * Device Tree Source for the R-Car H1 (R8A77790) SoC

 *

 * Copyright (C) 2013 Renesas Solutions Corp.

 * Copyright (C) 2013 Simon Horman
@@ -344,7 +344,7 @@ tmu2: timer@ffd82000 { 


	sata: sata@fc600000 {

		compatible = "renesas,sata-r8a7779", "renesas,rcar-sata";

		reg = <0xfc600000 0x2000>;

		reg = <0xfc600000 0x200000>;

		interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&mstp1_clks R8A7779_CLK_SATA>;

		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;

arch/arm/boot/dts/r8a7790-stout.dts

+4 −0
Original line number Diff line number Diff line
@@ -318,6 +318,10 @@ pmic@58 { 
		interrupts = <2 IRQ_TYPE_LEVEL_LOW>;

		interrupt-controller;



		onkey {

			compatible = "dlg,da9063-onkey";

		};



		rtc {

			compatible = "dlg,da9063-rtc";

		};