Commit 7adb6bab authored by Olof Johansson's avatar Olof Johansson
Browse files

Merge tag 'socfpga_updates_for_v4.20_part1' of... 

Merge tag 'socfpga_updates_for_v4.20_part1' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into next/dt

SoCFPGA DTS updates for v4.20
- Rename de0_sockit to de0_nano_soc
- Update NAND clocking
- Set timer interrupt to edge sensitive
- Stratix10 platform updates
  - Update devkit with correct i2c clock

* tag 'socfpga_updates_for_v4.20_part1' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux

:
  ARM: dts: socfpga: Rename socfpga_cyclone5_de0_{sockit,nano_soc}
  ARM: dts: socfpga: update NAND clocking for c5/a5
  ARM: dts: arria10: update NAND clocking
  ARM: dts: socfpga: set timer interrupt to edge sensitive
  ARM: dts: socfpga: use stdout-path for chosen node
  arm64: dts: stratix10: i2c clock running out of spec

Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents 57361846 202eb548

arch/arm/boot/dts/Makefile

+1 −1
Original line number Diff line number Diff line
@@ -892,7 +892,7 @@ dtb-$(CONFIG_ARCH_SOCFPGA) += \ 
	socfpga_arria10_socdk_sdmmc.dtb \

	socfpga_cyclone5_mcvevk.dtb \

	socfpga_cyclone5_socdk.dtb \

	socfpga_cyclone5_de0_sockit.dtb \

	socfpga_cyclone5_de0_nano_soc.dtb \

	socfpga_cyclone5_sockit.dtb \

	socfpga_cyclone5_socrates.dtb \

	socfpga_cyclone5_sodia.dtb \

arch/arm/boot/dts/socfpga.dtsi

+10 −2
Original line number Diff line number Diff line
@@ -483,10 +483,17 @@ nand_x_clk: nand_x_clk { 
						clk-gate = <0xa0 9>;

					};



					nand_ecc_clk: nand_ecc_clk {

						#clock-cells = <0>;

						compatible = "altr,socfpga-gate-clk";

						clocks = <&nand_x_clk>;

						clk-gate = <0xa0 9>;

					};



					nand_clk: nand_clk {

						#clock-cells = <0>;

						compatible = "altr,socfpga-gate-clk";

						clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;

						clocks = <&nand_x_clk>;

						clk-gate = <0xa0 10>;

						fixed-divider = <4>;

					};
@@ -754,7 +761,8 @@ nand0: nand@ff900000 { 
			reg-names = "nand_data", "denali_reg";

			interrupts = <0x0 0x90 0x4>;

			dma-mask = <0xffffffff>;

			clocks = <&nand_x_clk>;

			clocks = <&nand_clk>, <&nand_x_clk>, <&nand_ecc_clk>;

			clock-names = "nand", "nand_x", "ecc";

			status = "disabled";

		};

arch/arm/boot/dts/socfpga_arria10.dtsi

+19 −3
Original line number Diff line number Diff line
@@ -377,13 +377,28 @@ qspi_clk: qspi_clk { 
						clk-gate = <0xC8 11>;

					};



					nand_clk: nand_clk {

					nand_x_clk: nand_x_clk {

						#clock-cells = <0>;

						compatible = "altr,socfpga-a10-gate-clk";

						clocks = <&l4_mp_clk>;

						clk-gate = <0xC8 10>;

					};



					nand_ecc_clk: nand_ecc_clk {

						#clock-cells = <0>;

						compatible = "altr,socfpga-a10-gate-clk";

						clocks = <&nand_x_clk>;

						clk-gate = <0xC8 10>;

					};



					nand_clk: nand_clk {

						#clock-cells = <0>;

						compatible = "altr,socfpga-a10-gate-clk";

						clocks = <&nand_x_clk>;

						fixed-divider = <4>;

						clk-gate = <0xC8 10>;

					};



					spi_m_clk: spi_m_clk {

						#clock-cells = <0>;

						compatible = "altr,socfpga-a10-gate-clk";
@@ -650,7 +665,8 @@ nand: nand@ffb90000 { 
			reg-names = "nand_data", "denali_reg";

			interrupts = <0 99 4>;

			dma-mask = <0xffffffff>;

			clocks = <&nand_clk>;

			clocks = <&nand_clk>, <&nand_x_clk>, <&nand_ecc_clk>;

			clock-names = "nand", "nand_x", "ecc";

			status = "disabled";

		};
@@ -760,7 +776,7 @@ sysmgr: sysmgr@ffd06000 { 
		timer@ffffc600 {

			compatible = "arm,cortex-a9-twd-timer";

			reg = <0xffffc600 0x100>;

			interrupts = <1 13 0xf04>;

			interrupts = <1 13 0xf01>;

			clocks = <&mpu_periph_clk>;

		};

arch/arm/boot/dts/socfpga_cyclone5_socrates.dts

+2 −1
Original line number Diff line number Diff line
@@ -22,7 +22,8 @@ / { 
	compatible = "ebv,socrates", "altr,socfpga-cyclone5", "altr,socfpga";



	chosen {

		bootargs = "console=ttyS0,115200";

		bootargs = "earlyprintk";

		stdout-path = "serial0:115200n8";

	};



	memory@0 {