Commit fa00d6dc authored by Biju Das's avatar Biju Das Committed by Geert Uytterhoeven
Browse files

arm64: dts: renesas: rzg2lc-smarc: Enable SCIF1 on carrier board



SCIF1 interface is available on PMOD1 connector (CN7) on carrier board.

This patch adds pinmux and scif1 node to carrier board dtsi file for
RZ/G2LC SMARC EVK.

Signed-off-by: default avatarBiju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: default avatarLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20220203170636.7747-4-biju.das.jz@bp.renesas.com


Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent 2ed3b5d9
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+7 −0
Original line number Diff line number Diff line
@@ -17,6 +17,13 @@ scif0_pins: scif0 {
			 <RZG2L_PORT_PINMUX(38, 1, 1)>;	/* RxD */
	};

	scif1_pins: scif1 {
		pinmux = <RZG2L_PORT_PINMUX(40, 0, 1)>, /* TxD */
			 <RZG2L_PORT_PINMUX(40, 1, 1)>, /* RxD */
			 <RZG2L_PORT_PINMUX(41, 0, 1)>, /* CTS# */
			 <RZG2L_PORT_PINMUX(41, 1, 1)>; /* RTS# */
	};

	sd1-pwr-en-hog {
		gpio-hog;
		gpios = <RZG2L_GPIO(39, 2) GPIO_ACTIVE_HIGH>;
+26 −0
Original line number Diff line number Diff line
@@ -34,3 +34,29 @@
#include "rzg2lc-smarc-som.dtsi"
#include "rzg2lc-smarc-pinfunction.dtsi"
#include "rz-smarc-common.dtsi"

/* comment the #define statement to disable SCIF1 (SER0) on PMOD1 (CN7) */
#define PMOD1_SER0	1

/ {
	aliases {
		serial1 = &scif1;
	};
};

/*
 * To enable SCIF1 (SER0) on PMOD1 (CN7), On connector board
 * SW1 should be at position 2->3 so that SER0_CTS# line is activated
 * SW2 should be at position 2->3 so that SER0_TX line is activated
 * SW3 should be at position 2->3 so that SER0_RX line is activated
 * SW4 should be at position 2->3 so that SER0_RTS# line is activated
 */
#if (!SW_SCIF_CAN && PMOD1_SER0)
&scif1 {
	pinctrl-0 = <&scif1_pins>;
	pinctrl-names = "default";

	uart-has-rtscts;
	status = "okay";
};
#endif