Commit 5a8aa63c authored by Lad Prabhakar's avatar Lad Prabhakar Committed by Geert Uytterhoeven
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arm64: dts: renesas: rzg2l-smarc: Enable SCIF2 on carrier board 



SCIF2 interface is available on PMOD1 connector (CN7) on carrier board,
This patch adds pinmux and scif2 node to carrier board dtsi file.

Signed-off-by: default avatarLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: default avatarBiju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20211103195600.23964-4-prabhakar.mahadev-lad.rj@bp.renesas.com


Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent 68f8eb19

arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi

+28 −0
Original line number Diff line number Diff line
@@ -21,9 +21,13 @@ 
 *

 */



/* comment the #define statement to disable SCIF2 (SER0) on PMOD1 (CN7) */

#define PMOD1_SER0	1



/ {

	aliases {

		serial0 = &scif0;

		serial1 = &scif2;

		i2c0 = &i2c0;

		i2c1 = &i2c1;

		i2c3 = &i2c3;
@@ -208,6 +212,13 @@ scif0_pins: scif0 { 
			 <RZG2L_PORT_PINMUX(38, 1, 1)>;	/* RxD */

	};



	scif2_pins: scif2 {

		pinmux = <RZG2L_PORT_PINMUX(48, 0, 1)>, /* TxD */

			 <RZG2L_PORT_PINMUX(48, 1, 1)>, /* RxD */

			 <RZG2L_PORT_PINMUX(48, 3, 1)>, /* CTS# */

			 <RZG2L_PORT_PINMUX(48, 4, 1)>; /* RTS# */

	};



	sd1-pwr-en-hog {

		gpio-hog;

		gpios = <RZG2L_GPIO(39, 2) GPIO_ACTIVE_HIGH>;
@@ -277,6 +288,23 @@ &scif0 { 
	status = "okay";

};



/*

 * To enable SCIF2 (SER0) on PMOD1 (CN7)

 * SW1 should be at position 2->3 so that SER0_CTS# line is activated

 * SW2 should be at position 2->3 so that SER0_TX line is activated

 * SW3 should be at position 2->3 so that SER0_RX line is activated

 * SW4 should be at position 2->3 so that SER0_RTS# line is activated

 */

#if PMOD1_SER0

&scif2 {

	pinctrl-0 = <&scif2_pins>;

	pinctrl-names = "default";



	uart-has-rtscts;

	status = "okay";

};

#endif



&sdhi1 {

	pinctrl-0 = <&sdhi1_pins>;

	pinctrl-1 = <&sdhi1_pins_uhs>;