Commit f89dcb24 authored by Manivannan Sadhasivam's avatar Manivannan Sadhasivam Committed by Vinod Koul
Browse files

phy: qcom-qmp-ufs: Add HS G4 mode support to SM8150 SoC 



UFS PHY in SM8150 SoC is capable of operating at HS G4 mode. Hence, add the
required register settings using the tables_hs_g4 struct instance.

Reviewed-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Tested-by: Andrew Halaney <ahalaney@redhat.com> # Qdrive3/sa8540p-ride
Signed-off-by: default avatarManivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20230114071009.88102-8-manivannan.sadhasivam@linaro.org


Signed-off-by: default avatarVinod Koul <vkoul@kernel.org>
parent 0cf7620e

drivers/phy/qualcomm/phy-qcom-qmp-ufs.c

+36 −0
Original line number Diff line number Diff line
@@ -379,6 +379,10 @@ static const struct qmp_phy_init_tbl sm8150_ufsphy_tx[] = { 
	QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0c),

};



static const struct qmp_phy_init_tbl sm8150_ufsphy_hs_g4_tx[] = {

	QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x75),

};



static const struct qmp_phy_init_tbl sm8150_ufsphy_rx[] = {

	QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_LVL, 0x24),

	QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x0f),
@@ -416,6 +420,25 @@ static const struct qmp_phy_init_tbl sm8150_ufsphy_rx[] = { 
	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1),

};



static const struct qmp_phy_init_tbl sm8150_ufsphy_hs_g4_rx[] = {

	QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a),

	QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x81),

	QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0e),

	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x6f),

	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x20),

	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0x80),

	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x01),

	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x3f),

	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff),

	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff),

	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),

	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x6c),

	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x6d),

	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0x6d),

	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xed),

	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x3c),

};



static const struct qmp_phy_init_tbl sm8150_ufsphy_pcs[] = {

	QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_SIGDET_CTRL2, 0x6d),

	QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a),
@@ -426,6 +449,11 @@ static const struct qmp_phy_init_tbl sm8150_ufsphy_pcs[] = { 
	QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_MULTI_LANE_CTRL1, 0x02),

};



static const struct qmp_phy_init_tbl sm8150_ufsphy_hs_g4_pcs[] = {

	QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x10),

	QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_BIST_FIXED_PAT_CTRL, 0x0a),

};



static const struct qmp_phy_init_tbl sm8350_ufsphy_serdes[] = {

	QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0xd9),

	QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x11),
@@ -769,6 +797,14 @@ static const struct qmp_phy_cfg sm8150_ufsphy_cfg = { 
		.serdes		= sm8150_ufsphy_hs_b_serdes,

		.serdes_num	= ARRAY_SIZE(sm8150_ufsphy_hs_b_serdes),

	},

	.tbls_hs_g4 = {

		.tx		= sm8150_ufsphy_hs_g4_tx,

		.tx_num		= ARRAY_SIZE(sm8150_ufsphy_hs_g4_tx),

		.rx		= sm8150_ufsphy_hs_g4_rx,

		.rx_num		= ARRAY_SIZE(sm8150_ufsphy_hs_g4_rx),

		.pcs		= sm8150_ufsphy_hs_g4_pcs,

		.pcs_num	= ARRAY_SIZE(sm8150_ufsphy_hs_g4_pcs),

	},

	.clk_list		= sdm845_ufs_phy_clk_l,

	.num_clks		= ARRAY_SIZE(sdm845_ufs_phy_clk_l),

	.vreg_list		= qmp_phy_vreg_l,