Commit f1eb0456 authored Aug 01, 2023 by Duncan Ma Committed by Alex Deucher Sep 20, 2023

drm/amd/display: Fix dig register undefined



[Why]
Some of the stream encoder registers have register offset address 0. It
is causing no display in some scenarios due to DIG_FE was not setup
correctly and was not enabled.

[How]
Fix stream encoder register define list.

Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Reviewed-by: Charlene Liu <charlene.liu@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Duncan Ma <duncan.ma@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

parent 1101185b

drivers/gpu/drm/amd/display/dc/dcn35/dcn35_resource.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -308,7 +308,7 @@ static const struct dcn31_apg_mask apg_mask = {
		};

		#define stream_enc_regs_init(id)\
		SE_DCN32_REG_LIST_RI(id)
		SE_DCN35_REG_LIST_RI(id)

		static struct dcn10_stream_enc_registers stream_enc_regs[5];