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Commit efded37b authored by Phil Edworthy's avatar Phil Edworthy Committed by Geert Uytterhoeven
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clk: renesas: r9a09g011: Add WDT clock and reset entries 



Add WDT0 clock and reset entries to CPG driver.

Signed-off-by: default avatarPhil Edworthy <phil.edworthy@renesas.com>
Link: https://lore.kernel.org/r/20220518150105.48167-1-phil.edworthy@renesas.com


Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent e55c4481
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